mirror of https://github.com/torvalds/linux.git
dt-bindings: edac: altera: socfpga: Convert to YAML
Convert the device tree bindings for the Altera SoCFPGA ECC Manager from text to yaml. Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Link: https://lore.kernel.org/r/20250325173139.27634-1-matthew.gerlach@altera.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Matthew Gerlach
Rob Herring (Arm)
parent
18ddd99a01
commit
dd7af14795
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2025 Altera Corporation
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera SoCFPGA ECC Manager
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maintainers:
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- Matthew Gerlach <matthew.gerlach@altera.com>
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description:
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This binding describes the device tree nodes required for the Altera SoCFPGA
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ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
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families.
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-s10-ecc-manager
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- const: altr,socfpga-a10-ecc-manager
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- const: altr,socfpga-a10-ecc-manager
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- const: altr,socfpga-ecc-manager
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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ranges: true
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altr,sysmgr-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to Stratix10 System Manager Block with the ECC manager registers
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sdramedac:
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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- altr,sdram-edac-a10
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- altr,sdram-edac-s10
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interrupts:
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minItems: 1
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maxItems: 2
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altr,sdr-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to SDRAM parent
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required:
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- compatible
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- interrupts
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- altr,sdr-syscon
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patternProperties:
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"^ocram-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-s10-ocram-ecc
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- const: altr,socfpga-a10-ocram-ecc
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- const: altr,socfpga-a10-ocram-ecc
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- const: altr,socfpga-ocram-ecc
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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iram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to OCRAM parent
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altr,ecc-parent:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to OCRAM parent
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required:
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- compatible
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- reg
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- interrupts
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"^usb[0-9]-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-s10-usb-ecc
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- const: altr,socfpga-usb-ecc
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- const: altr,socfpga-usb-ecc
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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altr,ecc-parent:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to USB parent
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required:
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- compatible
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- reg
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- interrupts
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- altr,ecc-parent
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"^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-s10-eth-mac-ecc
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- const: altr,socfpga-eth-mac-ecc
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- const: altr,socfpga-eth-mac-ecc
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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altr,ecc-parent:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to ethernet parent
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required:
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- compatible
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- reg
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- interrupts
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- altr,ecc-parent
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"^sdmmc[a-f]-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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- items:
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- const: altr,socfpga-s10-sdmmc-ecc
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- const: altr,socfpga-sdmmc-ecc
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- const: altr,socfpga-sdmmc-ecc
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reg:
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maxItems: 1
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interrupts:
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minItems: 2
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maxItems: 4
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altr,ecc-parent:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to SD/MMC parent
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required:
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- compatible
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- reg
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- interrupts
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- altr,ecc-parent
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"^l2-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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- altr,socfpga-a10-l2-ecc
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- altr,socfpga-l2-ecc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 2
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required:
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- compatible
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- reg
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- interrupts
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"^dma-ecc@[a-f0-9]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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const: altr,socfpga-dma-ecc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 2
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altr,ecc-parent:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to SD/MMC parent
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required:
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- compatible
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- reg
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- interrupts
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- altr,ecc-parent
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if:
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properties:
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compatible:
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contains:
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const: altr,socfpga-ecc-manager
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then:
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- ranges
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else:
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- ranges
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- altr,sysmgr-syscon
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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eccmgr {
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compatible = "altr,socfpga-s10-ecc-manager",
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"altr,socfpga-a10-ecc-manager";
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altr,sysmgr-syscon = <&sysmgr>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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sdramedac {
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compatible = "altr,sdram-edac-s10";
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altr,sdr-syscon = <&sdr>;
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocram-ecc@ff8cc000 {
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compatible = "altr,socfpga-s10-ocram-ecc",
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"altr,socfpga-a10-ocram-ecc";
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reg = <0xff8cc000 0x100>;
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altr,ecc-parent = <&ocram>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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};
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usb0-ecc@ff8c4000 {
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compatible = "altr,socfpga-s10-usb-ecc",
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"altr,socfpga-usb-ecc";
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reg = <0xff8c4000 0x100>;
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altr,ecc-parent = <&usb0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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};
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emac0-rx-ecc@ff8c0000 {
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compatible = "altr,socfpga-s10-eth-mac-ecc",
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"altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0000 0x100>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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emac0-tx-ecc@ff8c0400 {
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compatible = "altr,socfpga-s10-eth-mac-ecc",
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"altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0400 0x100>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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};
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sdmmca-ecc@ff8c8c00 {
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compatible = "altr,socfpga-s10-sdmmc-ecc",
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"altr,socfpga-sdmmc-ecc";
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reg = <0xff8c8c00 0x100>;
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altr,ecc-parent = <&mmc>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
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<15 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -1,383 +0,0 @@
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Altera SoCFPGA ECC Manager
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This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Cyclone5 and Arria5 ECC Manager
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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On Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-ocram-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- iram : phandle to On-Chip RAM definition.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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Example:
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eccmgr: eccmgr@ffd08140 {
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compatible = "altr,socfpga-ecc-manager";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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l2-ecc@ffd08140 {
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compatible = "altr,socfpga-l2-ecc";
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reg = <0xffd08140 0x4>;
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interrupts = <0 36 1>, <0 37 1>;
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};
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ocram-ecc@ffd08144 {
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compatible = "altr,socfpga-ocram-ecc";
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reg = <0xffd08144 0x4>;
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iram = <&ocram>;
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interrupts = <0 178 1>, <0 179 1>;
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};
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};
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Arria10 SoCFPGA ECC Manager
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The Arria10 SoC ECC Manager handles the IRQs for each peripheral
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in a shared register instead of individual IRQs like the Cyclone5
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and Arria5. Therefore the device tree is different as well.
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ecc-manager"
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- altr,sysgr-syscon : phandle to Arria10 System Manager Block
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containing the ECC manager registers.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt.
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- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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- #interrupt-cells : must be set to 2.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Ethernet FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-eth-mac-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent Ethernet node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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NAND FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-nand-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent NAND node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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DMA FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-dma-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent DMA node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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USB FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-usb-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent USB node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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QSPI FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-qspi-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent QSPI node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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SDMMC FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-sdmmc-ecc"
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||||
- reg : Address and size for ECC block registers.
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||||
- altr,ecc-parent : phandle to parent SD/MMC node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order for port A, and then single bit error interrupt,
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then double bit error interrupt in this order for port B.
|
||||
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Example:
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eccmgr: eccmgr@ffd06000 {
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compatible = "altr,socfpga-a10-ecc-manager";
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altr,sysmgr-syscon = <&sysmgr>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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||||
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
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<32 IRQ_TYPE_LEVEL_HIGH>;
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||||
};
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||||
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
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<33 IRQ_TYPE_LEVEL_HIGH> ;
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||||
};
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||||
|
||||
emac0-rx-ecc@ff8c0800 {
|
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compatible = "altr,socfpga-eth-mac-ecc";
|
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reg = <0xff8c0800 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
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||||
|
||||
emac0-tx-ecc@ff8c0c00 {
|
||||
compatible = "altr,socfpga-eth-mac-ecc";
|
||||
reg = <0xff8c0c00 0x400>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-buf-ecc@ff8c2000 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2000 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-rd-ecc@ff8c2400 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2400 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-wr-ecc@ff8c2800 {
|
||||
compatible = "altr,socfpga-nand-ecc";
|
||||
reg = <0xff8c2800 0x400>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-dma-ecc";
|
||||
reg = <0xff8c8000 0x400>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb0-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-usb-ecc";
|
||||
reg = <0xff8c8800 0x400>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi-ecc@ff8c8400 {
|
||||
compatible = "altr,socfpga-qspi-ecc";
|
||||
reg = <0xff8c8400 0x400>;
|
||||
altr,ecc-parent = <&qspi>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmc-ecc@ff8c2c00 {
|
||||
compatible = "altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c2c00 0x400>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
Stratix10 SoCFPGA ECC Manager (ARM64)
|
||||
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
|
||||
in a shared register similar to the Arria10. However, Stratix10 ECC
|
||||
requires access to registers that can only be read from Secure Monitor
|
||||
with SMC calls. Therefore the device tree is slightly different. Note
|
||||
that only 1 interrupt is sent in Stratix10 because the double bit errors
|
||||
are treated as SErrors in ARM64 instead of IRQs in ARM32.
|
||||
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ecc-manager"
|
||||
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
|
||||
containing the ECC manager registers.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
|
||||
- #interrupt-cells : must be set to 2.
|
||||
- #address-cells: must be 1
|
||||
- #size-cells: must be 1
|
||||
- ranges : standard definition, should translate from local addresses
|
||||
|
||||
Subcomponents:
|
||||
|
||||
SDRAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,sdram-edac-s10"
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
On-Chip RAM ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent OCRAM node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
Ethernet FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent Ethernet node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
NAND FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-nand-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent NAND node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
DMA FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-dma-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent DMA node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
USB FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-usb-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent USB node.
|
||||
- interrupts : Should be single bit error interrupt.
|
||||
|
||||
SDMMC FIFO ECC
|
||||
Required Properties:
|
||||
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
|
||||
- reg : Address and size for ECC block registers.
|
||||
- altr,ecc-parent : phandle to parent SD/MMC node.
|
||||
- interrupts : Should be single bit error interrupt for port A
|
||||
and then single bit error interrupt for port B.
|
||||
|
||||
Example:
|
||||
|
||||
eccmgr {
|
||||
compatible = "altr,socfpga-s10-ecc-manager";
|
||||
altr,sysmgr-syscon = <&sysmgr>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <0 15 4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac-s10";
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocram-ecc@ff8cc000 {
|
||||
compatible = "altr,socfpga-s10-ocram-ecc";
|
||||
reg = <ff8cc000 0x100>;
|
||||
altr,ecc-parent = <&ocram>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-rx-ecc@ff8c0000 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0000 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emac0-tx-ecc@ff8c0400 {
|
||||
compatible = "altr,socfpga-s10-eth-mac-ecc";
|
||||
reg = <0xff8c0400 0x100>;
|
||||
altr,ecc-parent = <&gmac0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
|
||||
};
|
||||
|
||||
nand-buf-ecc@ff8c8000 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8000 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-rd-ecc@ff8c8400 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8400 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
nand-wr-ecc@ff8c8800 {
|
||||
compatible = "altr,socfpga-s10-nand-ecc";
|
||||
reg = <0xff8c8800 0x100>;
|
||||
altr,ecc-parent = <&nand>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma-ecc@ff8c9000 {
|
||||
compatible = "altr,socfpga-s10-dma-ecc";
|
||||
reg = <0xff8c9000 0x100>;
|
||||
altr,ecc-parent = <&pdma>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
usb0-ecc@ff8c4000 {
|
||||
compatible = "altr,socfpga-s10-usb-ecc";
|
||||
reg = <0xff8c4000 0x100>;
|
||||
altr,ecc-parent = <&usb0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdmmc-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3133,6 +3133,11 @@ M: Dinh Nguyen <dinguyen@kernel.org>
|
|||
S: Maintained
|
||||
F: drivers/clk/socfpga/
|
||||
|
||||
ARM/SOCFPGA EDAC BINDINGS
|
||||
M: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
|
||||
|
||||
ARM/SOCFPGA EDAC SUPPORT
|
||||
M: Dinh Nguyen <dinguyen@kernel.org>
|
||||
S: Maintained
|
||||
|
|
|
|||
Loading…
Reference in New Issue