mirror of https://github.com/torvalds/linux.git
- Fix CPU type in DT for econet
- Fix for Malta PCI MMIO breakage for SOC-it - Fix TLB shutdown caused by iniital uniquification - Fix random seg faults -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmkiIKQaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHA+4A//VBaGVDaIbqwE1xzBdeUQ j5yK4l9wbD4LO67DTN4eElouct/o48I1UbQSK3vBaBRlGKLEFK/2Pu1amh6VGWr9 SyI14AYlj0vX7C6nqSrGKL+/+1mA9pCQmpz4yshn+qnwoAqHjqs+enX3BiBh+L0j 1JJRyr8qGzQ8Xma80Bx5Jvst61a5AgQZvVf70nr/0LdoqjBkS6dqVKRHtA7VOqWd SqX1/y7FeLt6oPmzRYCy7Kp7RNDJ9sIht7ZklznV1tUBdDTRpA8eUqeSSyUEe0/7 x79jj3/On7vg84shs3u+JU8jjrVuyXQcSJq2YRw9kEm0lJ2nd2YFS13SpnT4ZMNQ qCyzfTELLQ+NvRNaiUWWj5RXdiSo2LrZNq/Qu2EsNaSz2YYkkmrAurGOd8rOcfka 59lKvoQ18Vt3Ok5EeaatAWANJhXpEodvScuGdzBocaJ8/mSBwUzd6Vit9fma6eJ2 o1evxG7rqhXo+fT3pfjkW9ueAzCwJvF+tXV47Ga3PLssZfBvGo90LhaMf8C+VQA+ WoSAHhHlhrjhpo0/8/Z5577LV0IyRhwcnoivphBAwuCNe6SQrkKDrnx6xbemwbM1 biCbMaknli72c/KfptoOtBJYyZdEkgCigsB9unBHFXtExreoCo0PEAoJIv0GZs4M 3y7EIgkwib7OZCU2cA4/hkA= =caJE -----END PGP SIGNATURE----- Merge tag 'mips-fixes_6.18_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - Fix CPU type in DT for econet - Fix for Malta PCI MMIO breakage for SOC-it - Fix TLB shutdown caused by iniital uniquification - Fix random seg faults due to missed vdso storage requirement * tag 'mips-fixes_6.18_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: kernel: Fix random segmentation faults MIPS: mm: Prevent a TLB shutdown on initial uniquification mips: dts: econet: fix EN751221 core type MIPS: Malta: Fix !EVA SOC-it PCI MMIO
This commit is contained in:
Linus Torvalds
commit
d13f3ac64e
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@ -18,7 +18,7 @@ cpus: cpus {
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips24KEc";
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compatible = "mips,mips34Kc";
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reg = <0>;
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};
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};
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@ -692,7 +692,7 @@ unsigned long mips_stack_top(void)
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/* Space for the VDSO, data page & GIC user page */
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if (current->thread.abi) {
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top -= PAGE_ALIGN(current->thread.abi->vdso->size);
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top -= PAGE_SIZE;
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top -= VDSO_NR_PAGES * PAGE_SIZE;
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top -= mips_gic_present() ? PAGE_SIZE : 0;
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/* Space to randomize the VDSO base */
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@ -15,6 +15,7 @@
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/export.h>
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#include <linux/sort.h>
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#include <asm/cpu.h>
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#include <asm/cpu-type.h>
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@ -508,54 +509,78 @@ static int __init set_ntlb(char *str)
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__setup("ntlb=", set_ntlb);
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/* Initialise all TLB entries with unique values */
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/* Comparison function for EntryHi VPN fields. */
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static int r4k_vpn_cmp(const void *a, const void *b)
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{
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long v = *(unsigned long *)a - *(unsigned long *)b;
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int s = sizeof(long) > sizeof(int) ? sizeof(long) * 8 - 1: 0;
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return s ? (v != 0) | v >> s : v;
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}
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/*
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* Initialise all TLB entries with unique values that do not clash with
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* what we have been handed over and what we'll be using ourselves.
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*/
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static void r4k_tlb_uniquify(void)
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{
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int entry = num_wired_entries();
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unsigned long tlb_vpns[1 << MIPS_CONF1_TLBS_SIZE];
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int tlbsize = current_cpu_data.tlbsize;
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int start = num_wired_entries();
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unsigned long vpn_mask;
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int cnt, ent, idx, i;
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vpn_mask = GENMASK(cpu_vmbits - 1, 13);
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vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
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htw_stop();
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for (i = start, cnt = 0; i < tlbsize; i++, cnt++) {
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unsigned long vpn;
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write_c0_index(i);
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mtc0_tlbr_hazard();
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tlb_read();
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tlb_read_hazard();
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vpn = read_c0_entryhi();
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vpn &= vpn_mask & PAGE_MASK;
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tlb_vpns[cnt] = vpn;
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/* Prevent any large pages from overlapping regular ones. */
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write_c0_pagemask(read_c0_pagemask() & PM_DEFAULT_MASK);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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}
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sort(tlb_vpns, cnt, sizeof(tlb_vpns[0]), r4k_vpn_cmp, NULL);
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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while (entry < current_cpu_data.tlbsize) {
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unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data);
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unsigned long asid = 0;
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int idx;
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idx = 0;
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ent = tlbsize;
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for (i = start; i < tlbsize; i++)
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while (1) {
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unsigned long entryhi, vpn;
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/* Skip wired MMID to make ginvt_mmid work */
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if (cpu_has_mmid)
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asid = MMID_KERNEL_WIRED + 1;
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entryhi = UNIQUE_ENTRYHI(ent);
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vpn = entryhi & vpn_mask & PAGE_MASK;
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/* Check for match before using UNIQUE_ENTRYHI */
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do {
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if (cpu_has_mmid) {
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write_c0_memorymapid(asid);
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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} else {
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write_c0_entryhi(UNIQUE_ENTRYHI(entry) | asid);
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}
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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/* No match or match is on current entry */
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if (idx < 0 || idx == entry)
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if (idx >= cnt || vpn < tlb_vpns[idx]) {
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write_c0_entryhi(entryhi);
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write_c0_index(i);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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ent++;
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break;
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/*
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* If we hit a match, we need to try again with
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* a different ASID.
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*/
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asid++;
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} while (asid < asid_mask);
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if (idx >= 0 && idx != entry)
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panic("Unable to uniquify TLB entry %d", idx);
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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entry++;
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}
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} else if (vpn == tlb_vpns[idx]) {
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ent++;
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} else {
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idx++;
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}
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}
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tlbw_use_hazard();
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htw_start();
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@ -602,6 +627,7 @@ static void r4k_tlb_configure(void)
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/* From this point on the ARC firmware is dead. */
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r4k_tlb_uniquify();
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local_flush_tlb_all();
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/* Did I tell you that ARC SUCKS? */
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}
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@ -241,16 +241,22 @@ void __init prom_init(void)
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#endif
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/*
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* Setup the Malta max (2GB) memory for PCI DMA in host bridge
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* in transparent addressing mode.
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* Set up memory mapping in host bridge for PCI DMA masters,
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* in transparent addressing mode. For EVA use the Malta
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* maximum of 2 GiB memory in the alias space at 0x80000000
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* as per PHYS_OFFSET. Otherwise use 256 MiB of memory in
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* the regular space, avoiding mapping the PCI MMIO window
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* for DMA as it seems to confuse the system controller's
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* logic, causing PCI MMIO to stop working.
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*/
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mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
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MSC_WRITE(MSC01_PCI_BAR0, mask);
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MSC_WRITE(MSC01_PCI_HEAD4, mask);
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mask = PHYS_OFFSET ? PHYS_OFFSET : 0xf0000000;
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MSC_WRITE(MSC01_PCI_BAR0,
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mask | PCI_BASE_ADDRESS_MEM_PREFETCH);
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MSC_WRITE(MSC01_PCI_HEAD4,
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PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH);
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mask &= MSC01_PCI_BAR0_SIZE_MSK;
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MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
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MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
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MSC_WRITE(MSC01_PCI_P2SCMAPL, PHYS_OFFSET);
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/* Don't handle target retries indefinitely. */
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if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
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