mirror of https://github.com/torvalds/linux.git
ASoC: amd: ps: add ACP7.0 & ACP7.1 specific soundwire dma driver changes
Add SoundWire dma driver changes specific to ACP7.0 & ACP7.1 platforms. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://patch.msgid.link/20250207062819.1527184-15-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda
Mark Brown
parent
fde277dbcf
commit
c878d5c1a5
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@ -140,6 +140,47 @@
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#define ACP70_TIMEOUT 2000
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#define ACP70_SDW_HOST_WAKE_MASK 0x0C00000
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#define ACP70_SDW0_DMA_MAX_STREAMS 6
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#define ACP70_SDW1_DMA_MAX_STREAMS ACP70_SDW0_DMA_MAX_STREAMS
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#define ACP70_P1_AUDIO0_TX_THRESHOLD 0x8
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#define ACP70_P1_AUDIO1_TX_THRESHOLD 0x6
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#define ACP70_P1_AUDIO2_TX_THRESHOLD 0x4
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#define ACP70_P1_AUDIO0_RX_THRESHOLD 0x7
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#define ACP70_P1_AUDIO1_RX_THRESHOLD 0x5
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#define ACP70_P1_AUDIO2_RX_THRESHOLD 0x3
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#define ACP70_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
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#define ACP70_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
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/*
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* Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
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* in ACP_EXTENAL_INTR_CNTL1 register for ACP70/ACP71 platforms
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* Stream id IRQ Bit
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* 0 (SDW1_AUDIO0_TX) 8
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* 1 (SDW1_AUDIO1_TX) 6
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* 2 (SDW1_AUDIO2_TX) 4
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* 3 (SDW1_AUDIO0_RX) 7
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* 4 (SDW1_AUDIO1_RX) 5
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* 5 (SDW1_AUDIO2_RX) 3
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*/
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#define ACP70_SDW1_DMA_TX_IRQ_MASK(i) (ACP70_P1_AUDIO0_TX_THRESHOLD - (2 * (i)))
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#define ACP70_SDW1_DMA_RX_IRQ_MASK(i) (ACP70_P1_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
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#define ACP70_SW0_AUDIO0_TX_EN ACP_SW0_AUDIO0_TX_EN
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#define ACP70_SW0_AUDIO1_TX_EN ACP_SW0_AUDIO1_TX_EN
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#define ACP70_SW0_AUDIO2_TX_EN ACP_SW0_AUDIO2_TX_EN
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#define ACP70_SW0_AUDIO0_RX_EN ACP_SW0_AUDIO0_RX_EN
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#define ACP70_SW0_AUDIO1_RX_EN ACP_SW0_AUDIO1_RX_EN
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#define ACP70_SW0_AUDIO2_RX_EN ACP_SW0_AUDIO2_RX_EN
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#define ACP70_SW1_AUDIO0_TX_EN 0x0003C10
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#define ACP70_SW1_AUDIO1_TX_EN 0x0003C50
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#define ACP70_SW1_AUDIO2_TX_EN 0x0003C6C
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#define ACP70_SW1_AUDIO0_RX_EN 0x0003C88
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#define ACP70_SW1_AUDIO1_RX_EN 0x0003D28
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#define ACP70_SW1_AUDIO2_RX_EN 0x0003D44
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enum acp_config {
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ACP_CONFIG_0 = 0,
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ACP_CONFIG_1,
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@ -178,6 +219,15 @@ enum amd_acp63_sdw1_channel {
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ACP63_SDW1_AUDIO1_RX,
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};
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enum amd_acp70_sdw_channel {
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ACP70_SDW_AUDIO0_TX = 0,
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ACP70_SDW_AUDIO1_TX,
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ACP70_SDW_AUDIO2_TX,
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ACP70_SDW_AUDIO0_RX,
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ACP70_SDW_AUDIO1_RX,
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ACP70_SDW_AUDIO2_RX,
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};
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struct pdm_stream_instance {
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u16 num_pages;
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u16 channels;
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@ -199,6 +249,8 @@ struct sdw_dma_dev_data {
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u32 acp_rev;
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struct snd_pcm_substream *acp63_sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];
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struct snd_pcm_substream *acp63_sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];
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struct snd_pcm_substream *acp70_sdw0_dma_stream[ACP70_SDW0_DMA_MAX_STREAMS];
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struct snd_pcm_substream *acp70_sdw1_dma_stream[ACP70_SDW1_DMA_MAX_STREAMS];
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};
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struct acp_sdw_dma_stream {
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@ -75,6 +75,72 @@ static u32 acp63_sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {
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ACP_SW1_AUDIO1_RX_EN,
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};
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static struct sdw_dma_ring_buf_reg acp70_sdw0_dma_reg[ACP70_SDW0_DMA_MAX_STREAMS] = {
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{ACP_AUDIO0_TX_DMA_SIZE, ACP_AUDIO0_TX_FIFOADDR, ACP_AUDIO0_TX_FIFOSIZE,
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ACP_AUDIO0_TX_RINGBUFSIZE, ACP_AUDIO0_TX_RINGBUFADDR, ACP_AUDIO0_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO1_TX_DMA_SIZE, ACP_AUDIO1_TX_FIFOADDR, ACP_AUDIO1_TX_FIFOSIZE,
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ACP_AUDIO1_TX_RINGBUFSIZE, ACP_AUDIO1_TX_RINGBUFADDR, ACP_AUDIO1_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO2_TX_DMA_SIZE, ACP_AUDIO2_TX_FIFOADDR, ACP_AUDIO2_TX_FIFOSIZE,
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ACP_AUDIO2_TX_RINGBUFSIZE, ACP_AUDIO2_TX_RINGBUFADDR, ACP_AUDIO2_TX_INTR_WATERMARK_SIZE,
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ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO0_RX_DMA_SIZE, ACP_AUDIO0_RX_FIFOADDR, ACP_AUDIO0_RX_FIFOSIZE,
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ACP_AUDIO0_RX_RINGBUFSIZE, ACP_AUDIO0_RX_RINGBUFADDR, ACP_AUDIO0_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO1_RX_DMA_SIZE, ACP_AUDIO1_RX_FIFOADDR, ACP_AUDIO1_RX_FIFOSIZE,
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ACP_AUDIO1_RX_RINGBUFSIZE, ACP_AUDIO1_RX_RINGBUFADDR, ACP_AUDIO1_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_AUDIO2_RX_DMA_SIZE, ACP_AUDIO2_RX_FIFOADDR, ACP_AUDIO2_RX_FIFOSIZE,
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ACP_AUDIO2_RX_RINGBUFSIZE, ACP_AUDIO2_RX_RINGBUFADDR, ACP_AUDIO2_RX_INTR_WATERMARK_SIZE,
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ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH}
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};
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static struct sdw_dma_ring_buf_reg acp70_sdw1_dma_reg[ACP70_SDW1_DMA_MAX_STREAMS] = {
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{ACP_P1_AUDIO0_TX_DMA_SIZE, ACP_P1_AUDIO0_TX_FIFOADDR, ACP_P1_AUDIO0_TX_FIFOSIZE,
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ACP_P1_AUDIO0_TX_RINGBUFSIZE, ACP_P1_AUDIO0_TX_RINGBUFADDR,
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ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE,
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ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR,
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ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO2_TX_DMA_SIZE, ACP_P1_AUDIO2_TX_FIFOADDR, ACP_P1_AUDIO2_TX_FIFOSIZE,
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ACP_P1_AUDIO2_TX_RINGBUFSIZE, ACP_P1_AUDIO2_TX_RINGBUFADDR,
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ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO0_RX_DMA_SIZE, ACP_P1_AUDIO0_RX_FIFOADDR, ACP_P1_AUDIO0_RX_FIFOSIZE,
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ACP_P1_AUDIO0_RX_RINGBUFSIZE, ACP_P1_AUDIO0_RX_RINGBUFADDR,
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ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO1_RX_DMA_SIZE, ACP_P1_AUDIO1_RX_FIFOADDR, ACP_P1_AUDIO1_RX_FIFOSIZE,
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ACP_P1_AUDIO1_RX_RINGBUFSIZE, ACP_P1_AUDIO1_RX_RINGBUFADDR,
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ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
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{ACP_P1_AUDIO2_RX_DMA_SIZE, ACP_P1_AUDIO2_RX_FIFOADDR, ACP_P1_AUDIO2_RX_FIFOSIZE,
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ACP_P1_AUDIO2_RX_RINGBUFSIZE, ACP_P1_AUDIO2_RX_RINGBUFADDR,
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ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE,
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ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH}
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};
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static u32 acp70_sdw0_dma_enable_reg[ACP70_SDW0_DMA_MAX_STREAMS] = {
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ACP70_SW0_AUDIO0_TX_EN,
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ACP70_SW0_AUDIO1_TX_EN,
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ACP70_SW0_AUDIO2_TX_EN,
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ACP70_SW0_AUDIO0_RX_EN,
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ACP70_SW0_AUDIO1_RX_EN,
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ACP70_SW0_AUDIO2_RX_EN,
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};
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static u32 acp70_sdw1_dma_enable_reg[ACP70_SDW1_DMA_MAX_STREAMS] = {
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ACP70_SW1_AUDIO0_TX_EN,
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ACP70_SW1_AUDIO1_TX_EN,
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ACP70_SW1_AUDIO2_TX_EN,
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ACP70_SW1_AUDIO0_RX_EN,
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ACP70_SW1_AUDIO1_RX_EN,
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ACP70_SW1_AUDIO2_RX_EN,
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};
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static const struct snd_pcm_hardware acp63_sdw_hardware_playback = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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@ -200,6 +266,27 @@ static int acp63_configure_sdw_ringbuffer(void __iomem *acp_base, u32 stream_id,
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return -EINVAL;
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}
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break;
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case ACP70_PCI_REV:
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case ACP71_PCI_REV:
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switch (manager_instance) {
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case ACP_SDW0:
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reg_dma_size = acp70_sdw0_dma_reg[stream_id].reg_dma_size;
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reg_fifo_addr = acp70_sdw0_dma_reg[stream_id].reg_fifo_addr;
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reg_fifo_size = acp70_sdw0_dma_reg[stream_id].reg_fifo_size;
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reg_ring_buf_size = acp70_sdw0_dma_reg[stream_id].reg_ring_buf_size;
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reg_ring_buf_addr = acp70_sdw0_dma_reg[stream_id].reg_ring_buf_addr;
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break;
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case ACP_SDW1:
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reg_dma_size = acp70_sdw1_dma_reg[stream_id].reg_dma_size;
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reg_fifo_addr = acp70_sdw1_dma_reg[stream_id].reg_fifo_addr;
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reg_fifo_size = acp70_sdw1_dma_reg[stream_id].reg_fifo_size;
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reg_ring_buf_size = acp70_sdw1_dma_reg[stream_id].reg_ring_buf_size;
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reg_ring_buf_addr = acp70_sdw1_dma_reg[stream_id].reg_ring_buf_addr;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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@ -292,6 +379,32 @@ static int acp63_sdw_dma_hw_params(struct snd_soc_component *component,
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return -EINVAL;
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}
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break;
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case ACP70_PCI_REV:
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case ACP71_PCI_REV:
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switch (stream->instance) {
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case ACP_SDW0:
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sdw_data->acp70_sdw0_dma_stream[stream_id] = substream;
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water_mark_size_reg = acp70_sdw0_dma_reg[stream_id].water_mark_size_reg;
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acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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irq_mask = BIT(ACP70_SDW0_DMA_TX_IRQ_MASK(stream_id));
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else
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irq_mask = BIT(ACP70_SDW0_DMA_RX_IRQ_MASK(stream_id));
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break;
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case ACP_SDW1:
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sdw_data->acp70_sdw1_dma_stream[stream_id] = substream;
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acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL1;
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water_mark_size_reg = acp70_sdw1_dma_reg[stream_id].water_mark_size_reg;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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irq_mask = BIT(ACP70_SDW1_DMA_TX_IRQ_MASK(stream_id));
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else
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irq_mask = BIT(ACP70_SDW1_DMA_RX_IRQ_MASK(stream_id));
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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@ -335,6 +448,21 @@ static u64 acp63_sdw_get_byte_count(struct acp_sdw_dma_stream *stream, void __io
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goto POINTER_RETURN_BYTES;
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}
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break;
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case ACP70_PCI_REV:
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case ACP71_PCI_REV:
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switch (stream->instance) {
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case ACP_SDW0:
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pos_low_reg = acp70_sdw0_dma_reg[stream->stream_id].pos_low_reg;
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pos_high_reg = acp70_sdw0_dma_reg[stream->stream_id].pos_high_reg;
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break;
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case ACP_SDW1:
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pos_low_reg = acp70_sdw1_dma_reg[stream->stream_id].pos_low_reg;
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pos_high_reg = acp70_sdw1_dma_reg[stream->stream_id].pos_high_reg;
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break;
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default:
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goto POINTER_RETURN_BYTES;
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}
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break;
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default:
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goto POINTER_RETURN_BYTES;
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}
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@ -398,6 +526,19 @@ static int acp63_sdw_dma_close(struct snd_soc_component *component,
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return -EINVAL;
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}
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break;
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case ACP70_PCI_REV:
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case ACP71_PCI_REV:
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switch (stream->instance) {
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case ACP_SDW0:
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sdw_data->acp70_sdw0_dma_stream[stream->stream_id] = NULL;
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break;
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case ACP_SDW1:
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sdw_data->acp70_sdw1_dma_stream[stream->stream_id] = NULL;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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@ -430,6 +571,19 @@ static int acp63_sdw_dma_enable(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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break;
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case ACP70_PCI_REV:
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case ACP71_PCI_REV:
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switch (stream->instance) {
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case ACP_SDW0:
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sdw_dma_en_reg = acp70_sdw0_dma_enable_reg[stream_id];
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break;
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case ACP_SDW1:
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sdw_dma_en_reg = acp70_sdw1_dma_enable_reg[stream_id];
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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