mirror of https://github.com/torvalds/linux.git
Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next
* clk-imx: clk: imx95-blk-ctl: Save/restore registers when RPM routines are called clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 MCU CCU clk: sunxi-ng: div: support power-of-two dividers clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock clk: sunxi-ng: sun6i-rtc: Add A523 specifics * clk-ti: clk: keystone: sci-clk: use devm_kmemdup_array() clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled
This commit is contained in:
Stephen Boyd
commit
c1e102f349
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@ -19,6 +19,7 @@ properties:
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compatible:
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enum:
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- allwinner,sun55i-a523-ccu
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- allwinner,sun55i-a523-mcu-ccu
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- allwinner,sun55i-a523-r-ccu
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reg:
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@ -26,11 +27,11 @@ properties:
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clocks:
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minItems: 4
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maxItems: 5
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maxItems: 9
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clock-names:
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minItems: 4
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maxItems: 5
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maxItems: 9
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required:
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- "#clock-cells"
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@ -63,6 +64,38 @@ allOf:
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- const: iosc
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- const: losc-fanout
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- if:
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properties:
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compatible:
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enum:
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- allwinner,sun55i-a523-mcu-ccu
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then:
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properties:
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clocks:
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items:
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- description: High Frequency Oscillator (usually at 24MHz)
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- description: Low Frequency Oscillator (usually at 32kHz)
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- description: Internal Oscillator
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- description: Audio PLL (4x)
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- description: Peripherals PLL 0 (300 MHz output)
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- description: DSP module clock
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- description: MBUS clock
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- description: PRCM AHB clock
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- description: PRCM APB0 clock
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clock-names:
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items:
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- const: hosc
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- const: losc
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- const: iosc
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- const: pll-audio0-4x
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- const: pll-periph0-300m
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- const: dsp
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- const: mbus
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- const: r-ahb
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- const: r-apb0
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- if:
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properties:
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compatible:
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@ -36,6 +36,7 @@ struct imx95_blk_ctl {
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void __iomem *base;
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/* clock gate register */
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u32 clk_reg_restore;
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const struct imx95_blk_ctl_dev_data *pdata;
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};
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struct imx95_blk_ctl_clk_dev_data {
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@ -349,7 +350,6 @@ static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
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static int imx95_bc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct imx95_blk_ctl_dev_data *bc_data;
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struct imx95_blk_ctl *bc;
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struct clk_hw_onecell_data *clk_hw_data;
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struct clk_hw **hws;
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@ -379,25 +379,25 @@ static int imx95_bc_probe(struct platform_device *pdev)
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return ret;
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}
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bc_data = of_device_get_match_data(dev);
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if (!bc_data)
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bc->pdata = of_device_get_match_data(dev);
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if (!bc->pdata)
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return devm_of_platform_populate(dev);
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clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->num_clks),
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clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc->pdata->num_clks),
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GFP_KERNEL);
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if (!clk_hw_data)
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return -ENOMEM;
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if (bc_data->rpm_enabled) {
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if (bc->pdata->rpm_enabled) {
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devm_pm_runtime_enable(&pdev->dev);
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pm_runtime_resume_and_get(&pdev->dev);
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}
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clk_hw_data->num = bc_data->num_clks;
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clk_hw_data->num = bc->pdata->num_clks;
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hws = clk_hw_data->hws;
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for (i = 0; i < bc_data->num_clks; i++) {
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const struct imx95_blk_ctl_clk_dev_data *data = &bc_data->clk_dev_data[i];
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for (i = 0; i < bc->pdata->num_clks; i++) {
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const struct imx95_blk_ctl_clk_dev_data *data = &bc->pdata->clk_dev_data[i];
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void __iomem *reg = base + data->reg;
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if (data->type == CLK_MUX) {
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@ -439,7 +439,7 @@ static int imx95_bc_probe(struct platform_device *pdev)
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return 0;
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cleanup:
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for (i = 0; i < bc_data->num_clks; i++) {
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for (i = 0; i < bc->pdata->num_clks; i++) {
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if (IS_ERR_OR_NULL(hws[i]))
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continue;
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clk_hw_unregister(hws[i]);
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@ -453,15 +453,24 @@ static int imx95_bc_runtime_suspend(struct device *dev)
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{
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struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
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bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);
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clk_disable_unprepare(bc->clk_apb);
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return 0;
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}
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static int imx95_bc_runtime_resume(struct device *dev)
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{
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struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
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int ret;
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return clk_prepare_enable(bc->clk_apb);
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ret = clk_prepare_enable(bc->clk_apb);
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if (ret)
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return ret;
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writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);
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return 0;
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}
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#endif
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@ -469,22 +478,12 @@ static int imx95_bc_runtime_resume(struct device *dev)
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static int imx95_bc_suspend(struct device *dev)
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{
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struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
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const struct imx95_blk_ctl_dev_data *bc_data;
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int ret;
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bc_data = of_device_get_match_data(dev);
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if (!bc_data)
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if (pm_runtime_suspended(dev))
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return 0;
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if (bc_data->rpm_enabled) {
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ret = pm_runtime_get_sync(bc->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(bc->dev);
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return ret;
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}
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}
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bc->clk_reg_restore = readl(bc->base + bc_data->clk_reg_offset);
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bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);
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clk_disable_unprepare(bc->clk_apb);
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return 0;
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}
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@ -492,16 +491,16 @@ static int imx95_bc_suspend(struct device *dev)
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static int imx95_bc_resume(struct device *dev)
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{
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struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
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const struct imx95_blk_ctl_dev_data *bc_data;
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int ret;
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bc_data = of_device_get_match_data(dev);
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if (!bc_data)
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if (pm_runtime_suspended(dev))
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return 0;
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writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset);
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ret = clk_prepare_enable(bc->clk_apb);
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if (ret)
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return ret;
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if (bc_data->rpm_enabled)
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pm_runtime_put(bc->dev);
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writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);
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return 0;
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}
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@ -480,13 +480,10 @@ static int ti_sci_scan_clocks_from_fw(struct sci_clk_provider *provider)
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num_clks++;
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}
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provider->clocks = devm_kmalloc_array(dev, num_clks, sizeof(sci_clk),
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GFP_KERNEL);
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provider->clocks = devm_kmemdup_array(dev, clks, num_clks, sizeof(sci_clk), GFP_KERNEL);
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if (!provider->clocks)
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return -ENOMEM;
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memcpy(provider->clocks, clks, num_clks * sizeof(sci_clk));
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provider->num_clocks = num_clks;
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devm_kfree(dev, clks);
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@ -57,6 +57,11 @@ config SUN55I_A523_CCU
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default ARCH_SUNXI
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depends on ARM64 || COMPILE_TEST
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config SUN55I_A523_MCU_CCU
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tristate "Support for the Allwinner A523/T527 MCU CCU"
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default ARCH_SUNXI
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depends on ARM64 || COMPILE_TEST
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config SUN55I_A523_R_CCU
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tristate "Support for the Allwinner A523/T527 PRCM CCU"
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default ARCH_SUNXI
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@ -34,6 +34,7 @@ obj-$(CONFIG_SUN50I_H6_CCU) += sun50i-h6-ccu.o
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obj-$(CONFIG_SUN50I_H6_R_CCU) += sun50i-h6-r-ccu.o
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obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
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obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o
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obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o
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obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o
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obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
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obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
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@ -61,6 +62,7 @@ sun50i-h6-ccu-y += ccu-sun50i-h6.o
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sun50i-h6-r-ccu-y += ccu-sun50i-h6-r.o
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sun50i-h616-ccu-y += ccu-sun50i-h616.o
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sun55i-a523-ccu-y += ccu-sun55i-a523.o
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sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o
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sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o
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sun4i-a10-ccu-y += ccu-sun4i-a10.o
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sun5i-ccu-y += ccu-sun5i.o
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|
|
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@ -0,0 +1,469 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
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*
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* Based on the A523 CCU driver:
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* Copyright (C) 2023-2024 Arm Ltd.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
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|
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#include "ccu_common.h"
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#include "ccu_reset.h"
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|
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#include "ccu_div.h"
|
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#include "ccu_gate.h"
|
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#include "ccu_mp.h"
|
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#include "ccu_mult.h"
|
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#include "ccu_nm.h"
|
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|
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static const struct clk_parent_data osc24M[] = {
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{ .fw_name = "hosc" }
|
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};
|
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|
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static const struct clk_parent_data ahb[] = {
|
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{ .fw_name = "r-ahb" }
|
||||
};
|
||||
|
||||
static const struct clk_parent_data apb[] = {
|
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{ .fw_name = "r-apb0" }
|
||||
};
|
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|
||||
#define SUN55I_A523_PLL_AUDIO1_REG 0x00c
|
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static struct ccu_sdm_setting pll_audio1_sdm_table[] = {
|
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{ .rate = 2167603200, .pattern = 0xa000a234, .m = 1, .n = 90 }, /* div2->22.5792 */
|
||||
{ .rate = 2359296000, .pattern = 0xa0009ba6, .m = 1, .n = 98 }, /* div2->24.576 */
|
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{ .rate = 1806336000, .pattern = 0xa000872b, .m = 1, .n = 75 }, /* div5->22.576 */
|
||||
};
|
||||
|
||||
static struct ccu_nm pll_audio1_clk = {
|
||||
.enable = BIT(27),
|
||||
.lock = BIT(28),
|
||||
.n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
|
||||
.m = _SUNXI_CCU_DIV(1, 1),
|
||||
.sdm = _SUNXI_CCU_SDM(pll_audio1_sdm_table, BIT(24),
|
||||
0x010, BIT(31)),
|
||||
.min_rate = 180000000U,
|
||||
.max_rate = 3500000000U,
|
||||
.common = {
|
||||
.reg = 0x00c,
|
||||
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
|
||||
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1",
|
||||
osc24M, &ccu_nm_ops,
|
||||
CLK_SET_RATE_GATE),
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* /2 and /5 dividers are actually programmable, but we just use the
|
||||
* values from the BSP, since the audio PLL only needs to provide a
|
||||
* couple clock rates. This also matches the names given in the manual.
|
||||
*/
|
||||
static const struct clk_hw *pll_audio1_div_parents[] = { &pll_audio1_clk.common.hw };
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
|
||||
pll_audio1_div_parents, 2, 1,
|
||||
CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
|
||||
pll_audio1_div_parents, 5, 1,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(audio_out_clk, "audio-out",
|
||||
"pll-audio1-div2", 0x01c,
|
||||
0, 5, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static const struct clk_parent_data dsp_parents[] = {
|
||||
{ .fw_name = "hosc" },
|
||||
{ .fw_name = "losc" },
|
||||
{ .fw_name = "iosc" },
|
||||
/*
|
||||
* The order of the following two parent is from the BSP code. It is
|
||||
* the opposite in the manual. Testing with the DSP is required to
|
||||
* figure out the real order.
|
||||
*/
|
||||
{ .hw = &pll_audio1_div5_clk.hw },
|
||||
{ .hw = &pll_audio1_div2_clk.hw },
|
||||
{ .fw_name = "dsp" },
|
||||
};
|
||||
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "mcu-dsp", dsp_parents, 0x0020,
|
||||
0, 5, /* M */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static const struct clk_parent_data i2s_parents[] = {
|
||||
{ .fw_name = "pll-audio0-4x" },
|
||||
{ .hw = &pll_audio1_div2_clk.hw },
|
||||
{ .hw = &pll_audio1_div5_clk.hw },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(i2s0_clk, "i2s0", i2s_parents, 0x02c,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(i2s1_clk, "i2s1", i2s_parents, 0x030,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(i2s2_clk, "i2s2", i2s_parents, 0x034,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_clk, "i2s3", i2s_parents, 0x038,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static const struct clk_parent_data i2s3_asrc_parents[] = {
|
||||
{ .fw_name = "pll-periph0-300m" },
|
||||
{ .hw = &pll_audio1_div2_clk.hw },
|
||||
{ .hw = &pll_audio1_div5_clk.hw },
|
||||
};
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_asrc_clk, "i2s3-asrc",
|
||||
i2s3_asrc_parents, 0x03c,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_i2s0_clk, "bus-i2s0", apb, 0x040, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_i2s1_clk, "bus-i2s1", apb, 0x040, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_i2s2_clk, "bus-i2s2", apb, 0x040, BIT(2), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_i2s3_clk, "bus-i2s3", apb, 0x040, BIT(3), 0);
|
||||
|
||||
static const struct clk_parent_data audio_parents[] = {
|
||||
{ .fw_name = "pll-audio0-4x" },
|
||||
{ .hw = &pll_audio1_div2_clk.hw },
|
||||
{ .hw = &pll_audio1_div5_clk.hw },
|
||||
};
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_tx_clk, "spdif-tx",
|
||||
audio_parents, 0x044,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_rx_clk, "spdif-rx",
|
||||
i2s3_asrc_parents, 0x048,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_spdif_clk, "bus-spdif", apb, 0x04c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(dmic_clk, "dmic", audio_parents, 0x050,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_dmic_clk, "bus-dmic", apb, 0x054, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(audio_dac_clk, "audio-dac",
|
||||
audio_parents, 0x058,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(audio_adc_clk, "audio-adc",
|
||||
audio_parents, 0x05c,
|
||||
0, 5, /* M */
|
||||
5, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_audio_codec_clk, "bus-audio-codec",
|
||||
apb, 0x060, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_dsp_msgbox_clk, "bus-dsp-msgbox",
|
||||
ahb, 0x068, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_dsp_cfg_clk, "bus-dsp-cfg",
|
||||
apb, 0x06c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", ahb, 0x070, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", ahb, 0x070, BIT(2), 0);
|
||||
|
||||
static const struct clk_parent_data timer_parents[] = {
|
||||
{ .fw_name = "hosc" },
|
||||
{ .fw_name = "losc" },
|
||||
{ .fw_name = "iosc" },
|
||||
{ .fw_name = "r-ahb" }
|
||||
};
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer0_clk, "mcu-timer0", timer_parents,
|
||||
0x074,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer1_clk, "mcu-timer1", timer_parents,
|
||||
0x078,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer2_clk, "mcu-timer2", timer_parents,
|
||||
0x07c,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer3_clk, "mcu-timer3", timer_parents,
|
||||
0x080,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer4_clk, "mcu-timer4", timer_parents,
|
||||
0x084,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer5_clk, "mcu-timer5", timer_parents,
|
||||
0x088,
|
||||
1, 3, /* P */
|
||||
4, 2, /* mux */
|
||||
BIT(0), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", ahb, 0x08c, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", ahb, 0x104, BIT(0), 0);
|
||||
/* tzma* only found in BSP code. */
|
||||
static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", ahb, 0x108, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", ahb, 0x10c, BIT(0), 0);
|
||||
/* parent is a guess as this block is not shown in the system bus tree diagram */
|
||||
static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", ahb, 0x114, BIT(0), 0);
|
||||
|
||||
/*
|
||||
* user manual has "mbus" clock as parent of both clocks below,
|
||||
* but this makes more sense, since BSP MCU DMA controller has
|
||||
* reference to both of them, likely needing both enabled.
|
||||
*/
|
||||
static SUNXI_CCU_GATE_FW(mbus_mcu_clk, "mbus-mcu", "mbus", 0x11c, BIT(1), 0);
|
||||
static SUNXI_CCU_GATE_HW(mbus_mcu_dma_clk, "mbus-mcu-dma",
|
||||
&mbus_mcu_clk.common.hw, 0x11c, BIT(0), 0);
|
||||
|
||||
static const struct clk_parent_data riscv_pwm_parents[] = {
|
||||
{ .fw_name = "hosc" },
|
||||
{ .fw_name = "losc" },
|
||||
{ .fw_name = "iosc" },
|
||||
};
|
||||
|
||||
static SUNXI_CCU_MUX_DATA_WITH_GATE(riscv_clk, "riscv",
|
||||
riscv_pwm_parents, 0x120,
|
||||
27, 3, BIT(31), 0);
|
||||
/* Parents are guesses as these two blocks are not shown in the system bus tree diagram */
|
||||
static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", ahb,
|
||||
0x124, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", ahb,
|
||||
0x128, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_MUX_DATA_WITH_GATE(mcu_pwm0_clk, "mcu-pwm0",
|
||||
riscv_pwm_parents, 0x130,
|
||||
24, 3, BIT(31), 0);
|
||||
static SUNXI_CCU_GATE_DATA(bus_mcu_pwm0_clk, "bus-mcu-pwm0", apb,
|
||||
0x134, BIT(0), 0);
|
||||
|
||||
/*
|
||||
* Contains all clocks that are controlled by a hardware register. They
|
||||
* have a (sunxi) .common member, which needs to be initialised by the common
|
||||
* sunxi CCU code, to be filled with the MMIO base address and the shared lock.
|
||||
*/
|
||||
static struct ccu_common *sun55i_a523_mcu_ccu_clks[] = {
|
||||
&pll_audio1_clk.common,
|
||||
&audio_out_clk.common,
|
||||
&dsp_clk.common,
|
||||
&i2s0_clk.common,
|
||||
&i2s1_clk.common,
|
||||
&i2s2_clk.common,
|
||||
&i2s3_clk.common,
|
||||
&i2s3_asrc_clk.common,
|
||||
&bus_i2s0_clk.common,
|
||||
&bus_i2s1_clk.common,
|
||||
&bus_i2s2_clk.common,
|
||||
&bus_i2s3_clk.common,
|
||||
&spdif_tx_clk.common,
|
||||
&spdif_rx_clk.common,
|
||||
&bus_spdif_clk.common,
|
||||
&dmic_clk.common,
|
||||
&bus_dmic_clk.common,
|
||||
&audio_dac_clk.common,
|
||||
&audio_adc_clk.common,
|
||||
&bus_audio_codec_clk.common,
|
||||
&bus_dsp_msgbox_clk.common,
|
||||
&bus_dsp_cfg_clk.common,
|
||||
&bus_npu_aclk.common,
|
||||
&bus_npu_hclk.common,
|
||||
&mcu_timer0_clk.common,
|
||||
&mcu_timer1_clk.common,
|
||||
&mcu_timer2_clk.common,
|
||||
&mcu_timer3_clk.common,
|
||||
&mcu_timer4_clk.common,
|
||||
&mcu_timer5_clk.common,
|
||||
&bus_mcu_timer_clk.common,
|
||||
&bus_mcu_dma_clk.common,
|
||||
&tzma0_clk.common,
|
||||
&tzma1_clk.common,
|
||||
&bus_pubsram_clk.common,
|
||||
&mbus_mcu_dma_clk.common,
|
||||
&mbus_mcu_clk.common,
|
||||
&riscv_clk.common,
|
||||
&bus_riscv_cfg_clk.common,
|
||||
&bus_riscv_msgbox_clk.common,
|
||||
&mcu_pwm0_clk.common,
|
||||
&bus_mcu_pwm0_clk.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun55i_a523_mcu_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_MCU_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
|
||||
[CLK_MCU_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.hw,
|
||||
[CLK_MCU_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.hw,
|
||||
[CLK_MCU_AUDIO_OUT] = &audio_out_clk.common.hw,
|
||||
[CLK_MCU_DSP] = &dsp_clk.common.hw,
|
||||
[CLK_MCU_I2S0] = &i2s0_clk.common.hw,
|
||||
[CLK_MCU_I2S1] = &i2s1_clk.common.hw,
|
||||
[CLK_MCU_I2S2] = &i2s2_clk.common.hw,
|
||||
[CLK_MCU_I2S3] = &i2s3_clk.common.hw,
|
||||
[CLK_MCU_I2S3_ASRC] = &i2s3_asrc_clk.common.hw,
|
||||
[CLK_BUS_MCU_I2S0] = &bus_i2s0_clk.common.hw,
|
||||
[CLK_BUS_MCU_I2S1] = &bus_i2s1_clk.common.hw,
|
||||
[CLK_BUS_MCU_I2S2] = &bus_i2s2_clk.common.hw,
|
||||
[CLK_BUS_MCU_I2S3] = &bus_i2s3_clk.common.hw,
|
||||
[CLK_MCU_SPDIF_TX] = &spdif_tx_clk.common.hw,
|
||||
[CLK_MCU_SPDIF_RX] = &spdif_rx_clk.common.hw,
|
||||
[CLK_BUS_MCU_SPDIF] = &bus_spdif_clk.common.hw,
|
||||
[CLK_MCU_DMIC] = &dmic_clk.common.hw,
|
||||
[CLK_BUS_MCU_DMIC] = &bus_dmic_clk.common.hw,
|
||||
[CLK_MCU_AUDIO_CODEC_DAC] = &audio_dac_clk.common.hw,
|
||||
[CLK_MCU_AUDIO_CODEC_ADC] = &audio_adc_clk.common.hw,
|
||||
[CLK_BUS_MCU_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
|
||||
[CLK_BUS_MCU_DSP_MSGBOX] = &bus_dsp_msgbox_clk.common.hw,
|
||||
[CLK_BUS_MCU_DSP_CFG] = &bus_dsp_cfg_clk.common.hw,
|
||||
[CLK_BUS_MCU_NPU_HCLK] = &bus_npu_hclk.common.hw,
|
||||
[CLK_BUS_MCU_NPU_ACLK] = &bus_npu_aclk.common.hw,
|
||||
[CLK_MCU_TIMER0] = &mcu_timer0_clk.common.hw,
|
||||
[CLK_MCU_TIMER1] = &mcu_timer1_clk.common.hw,
|
||||
[CLK_MCU_TIMER2] = &mcu_timer2_clk.common.hw,
|
||||
[CLK_MCU_TIMER3] = &mcu_timer3_clk.common.hw,
|
||||
[CLK_MCU_TIMER4] = &mcu_timer4_clk.common.hw,
|
||||
[CLK_MCU_TIMER5] = &mcu_timer5_clk.common.hw,
|
||||
[CLK_BUS_MCU_TIMER] = &bus_mcu_timer_clk.common.hw,
|
||||
[CLK_BUS_MCU_DMA] = &bus_mcu_dma_clk.common.hw,
|
||||
[CLK_MCU_TZMA0] = &tzma0_clk.common.hw,
|
||||
[CLK_MCU_TZMA1] = &tzma1_clk.common.hw,
|
||||
[CLK_BUS_MCU_PUBSRAM] = &bus_pubsram_clk.common.hw,
|
||||
[CLK_MCU_MBUS_DMA] = &mbus_mcu_dma_clk.common.hw,
|
||||
[CLK_MCU_MBUS] = &mbus_mcu_clk.common.hw,
|
||||
[CLK_MCU_RISCV] = &riscv_clk.common.hw,
|
||||
[CLK_BUS_MCU_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
|
||||
[CLK_BUS_MCU_RISCV_MSGBOX] = &bus_riscv_msgbox_clk.common.hw,
|
||||
[CLK_MCU_PWM0] = &mcu_pwm0_clk.common.hw,
|
||||
[CLK_BUS_MCU_PWM0] = &bus_mcu_pwm0_clk.common.hw,
|
||||
},
|
||||
.num = CLK_BUS_MCU_PWM0 + 1,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun55i_a523_mcu_ccu_resets[] = {
|
||||
[RST_BUS_MCU_I2S0] = { 0x0040, BIT(16) },
|
||||
[RST_BUS_MCU_I2S1] = { 0x0040, BIT(17) },
|
||||
[RST_BUS_MCU_I2S2] = { 0x0040, BIT(18) },
|
||||
[RST_BUS_MCU_I2S3] = { 0x0040, BIT(19) },
|
||||
[RST_BUS_MCU_SPDIF] = { 0x004c, BIT(16) },
|
||||
[RST_BUS_MCU_DMIC] = { 0x0054, BIT(16) },
|
||||
[RST_BUS_MCU_AUDIO_CODEC] = { 0x0060, BIT(16) },
|
||||
[RST_BUS_MCU_DSP_MSGBOX] = { 0x0068, BIT(16) },
|
||||
[RST_BUS_MCU_DSP_CFG] = { 0x006c, BIT(16) },
|
||||
[RST_BUS_MCU_NPU] = { 0x0070, BIT(16) },
|
||||
[RST_BUS_MCU_TIMER] = { 0x008c, BIT(16) },
|
||||
/* dsp and dsp_debug resets only found in BSP code. */
|
||||
[RST_BUS_MCU_DSP_DEBUG] = { 0x0100, BIT(16) },
|
||||
[RST_BUS_MCU_DSP] = { 0x0100, BIT(17) },
|
||||
[RST_BUS_MCU_DMA] = { 0x0104, BIT(16) },
|
||||
[RST_BUS_MCU_PUBSRAM] = { 0x0114, BIT(16) },
|
||||
[RST_BUS_MCU_RISCV_CFG] = { 0x0124, BIT(16) },
|
||||
[RST_BUS_MCU_RISCV_DEBUG] = { 0x0124, BIT(17) },
|
||||
[RST_BUS_MCU_RISCV_CORE] = { 0x0124, BIT(18) },
|
||||
[RST_BUS_MCU_RISCV_MSGBOX] = { 0x0128, BIT(16) },
|
||||
[RST_BUS_MCU_PWM0] = { 0x0134, BIT(16) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun55i_a523_mcu_ccu_desc = {
|
||||
.ccu_clks = sun55i_a523_mcu_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun55i_a523_mcu_ccu_clks),
|
||||
|
||||
.hw_clks = &sun55i_a523_mcu_hw_clks,
|
||||
|
||||
.resets = sun55i_a523_mcu_ccu_resets,
|
||||
.num_resets = ARRAY_SIZE(sun55i_a523_mcu_ccu_resets),
|
||||
};
|
||||
|
||||
static int sun55i_a523_mcu_ccu_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
reg = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
val = readl(reg + SUN55I_A523_PLL_AUDIO1_REG);
|
||||
|
||||
/*
|
||||
* The PLL clock code does not model all bits, for instance it does
|
||||
* not support a separate enable and gate bit. We present the
|
||||
* gate bit(27) as the enable bit, but then have to set the
|
||||
* PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here.
|
||||
*/
|
||||
val |= BIT(31) | BIT(30) | BIT(29);
|
||||
|
||||
/* Enforce p1 = 5, p0 = 2 (the default) for PLL_AUDIO1 */
|
||||
val &= ~(GENMASK(22, 20) | GENMASK(18, 16));
|
||||
val |= (4 << 20) | (1 << 16);
|
||||
|
||||
writel(val, reg + SUN55I_A523_PLL_AUDIO1_REG);
|
||||
|
||||
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_mcu_ccu_desc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id sun55i_a523_mcu_ccu_ids[] = {
|
||||
{ .compatible = "allwinner,sun55i-a523-mcu-ccu" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver sun55i_a523_mcu_ccu_driver = {
|
||||
.probe = sun55i_a523_mcu_ccu_probe,
|
||||
.driver = {
|
||||
.name = "sun55i-a523-mcu-ccu",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = sun55i_a523_mcu_ccu_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun55i_a523_mcu_ccu_driver);
|
||||
|
||||
MODULE_IMPORT_NS("SUNXI_CCU");
|
||||
MODULE_DESCRIPTION("Support for the Allwinner A523 MCU CCU");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -11,6 +11,9 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clock/sun55i-a523-ccu.h>
|
||||
#include <dt-bindings/reset/sun55i-a523-ccu.h>
|
||||
|
||||
#include "../clk.h"
|
||||
|
||||
#include "ccu_common.h"
|
||||
|
|
@ -25,8 +28,6 @@
|
|||
#include "ccu_nkmp.h"
|
||||
#include "ccu_nm.h"
|
||||
|
||||
#include "ccu-sun55i-a523.h"
|
||||
|
||||
/*
|
||||
* The 24 MHz oscillator, the root of most of the clock tree.
|
||||
* .fw_name is the string used in the DT "clock-names" property, used to
|
||||
|
|
@ -486,6 +487,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
|
|||
|
||||
static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
|
||||
|
||||
static const struct clk_hw *npu_parents[] = {
|
||||
&pll_periph0_480M_clk.common.hw,
|
||||
&pll_periph0_600M_clk.hw,
|
||||
&pll_periph0_800M_clk.common.hw,
|
||||
&pll_npu_2x_clk.hw,
|
||||
};
|
||||
static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
|
||||
0, 5, /* M */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,
|
||||
|
|
@ -1217,6 +1230,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
|
|||
&bus_ce_sys_clk.common,
|
||||
&ve_clk.common,
|
||||
&bus_ve_clk.common,
|
||||
&npu_clk.common,
|
||||
&bus_dma_clk.common,
|
||||
&bus_msgbox_clk.common,
|
||||
&bus_spinlock_clk.common,
|
||||
|
|
@ -1343,7 +1357,6 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
|
|||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
|
||||
.num = CLK_NUMBER,
|
||||
.hws = {
|
||||
[CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
|
||||
[CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
|
||||
|
|
@ -1524,7 +1537,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
|
|||
[CLK_FANOUT0] = &fanout0_clk.common.hw,
|
||||
[CLK_FANOUT1] = &fanout1_clk.common.hw,
|
||||
[CLK_FANOUT2] = &fanout2_clk.common.hw,
|
||||
[CLK_NPU] = &npu_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NPU + 1,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun55i_a523_ccu_resets[] = {
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2024 Arm Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUN55I_A523_H
|
||||
#define _CCU_SUN55I_A523_H
|
||||
|
||||
#include <dt-bindings/clock/sun55i-a523-ccu.h>
|
||||
#include <dt-bindings/reset/sun55i-a523-ccu.h>
|
||||
|
||||
#define CLK_NUMBER (CLK_FANOUT2 + 1)
|
||||
|
||||
#endif /* _CCU_SUN55I_A523_H */
|
||||
|
|
@ -325,6 +325,13 @@ static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = {
|
|||
.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
|
||||
};
|
||||
|
||||
static const struct sun6i_rtc_match_data sun55i_a523_rtc_ccu_data = {
|
||||
.have_ext_osc32k = true,
|
||||
.have_iosc_calibration = true,
|
||||
.osc32k_fanout_parents = sun50i_r329_osc32k_fanout_parents,
|
||||
.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
|
||||
};
|
||||
|
||||
static const struct of_device_id sun6i_rtc_ccu_match[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun50i-h616-rtc",
|
||||
|
|
@ -334,6 +341,10 @@ static const struct of_device_id sun6i_rtc_ccu_match[] = {
|
|||
.compatible = "allwinner,sun50i-r329-rtc",
|
||||
.data = &sun50i_r329_rtc_ccu_data,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun55i-a523-rtc",
|
||||
.data = &sun55i_a523_rtc_ccu_data,
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
|
||||
|
|
|
|||
|
|
@ -274,6 +274,24 @@ struct ccu_div {
|
|||
SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
|
||||
_mshift, _mwidth, 0, _flags)
|
||||
|
||||
#define SUNXI_CCU_P_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
|
||||
_mshift, _mwidth, \
|
||||
_muxshift, _muxwidth, \
|
||||
_gate, _flags) \
|
||||
struct ccu_div _struct = { \
|
||||
.enable = _gate, \
|
||||
.div = _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, \
|
||||
CLK_DIVIDER_POWER_OF_TWO), \
|
||||
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
|
||||
.common = { \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
|
||||
_parents, \
|
||||
&ccu_div_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_common *common = hw_to_ccu_common(hw);
|
||||
|
|
|
|||
|
|
@ -258,6 +258,8 @@ static const char *enable_init_clks[] = {
|
|||
"dpll_ddr_m2_ck",
|
||||
"dpll_mpu_m2_ck",
|
||||
"l3_gclk",
|
||||
/* WKUP_DEBUGSS_CLKCTRL - disable fails, AM335x Errata Advisory 1.0.42 */
|
||||
"l3-aon-clkctrl:0000:0",
|
||||
/* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */
|
||||
"l3-clkctrl:00bc:0",
|
||||
"l4hs_gclk",
|
||||
|
|
|
|||
|
|
@ -185,5 +185,6 @@
|
|||
#define CLK_FANOUT0 176
|
||||
#define CLK_FANOUT1 177
|
||||
#define CLK_FANOUT2 178
|
||||
#define CLK_NPU 179
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
|
||||
|
||||
#define CLK_MCU_PLL_AUDIO1 0
|
||||
#define CLK_MCU_PLL_AUDIO1_DIV2 1
|
||||
#define CLK_MCU_PLL_AUDIO1_DIV5 2
|
||||
#define CLK_MCU_AUDIO_OUT 3
|
||||
#define CLK_MCU_DSP 4
|
||||
#define CLK_MCU_I2S0 5
|
||||
#define CLK_MCU_I2S1 6
|
||||
#define CLK_MCU_I2S2 7
|
||||
#define CLK_MCU_I2S3 8
|
||||
#define CLK_MCU_I2S3_ASRC 9
|
||||
#define CLK_BUS_MCU_I2S0 10
|
||||
#define CLK_BUS_MCU_I2S1 11
|
||||
#define CLK_BUS_MCU_I2S2 12
|
||||
#define CLK_BUS_MCU_I2S3 13
|
||||
#define CLK_MCU_SPDIF_TX 14
|
||||
#define CLK_MCU_SPDIF_RX 15
|
||||
#define CLK_BUS_MCU_SPDIF 16
|
||||
#define CLK_MCU_DMIC 17
|
||||
#define CLK_BUS_MCU_DMIC 18
|
||||
#define CLK_MCU_AUDIO_CODEC_DAC 19
|
||||
#define CLK_MCU_AUDIO_CODEC_ADC 20
|
||||
#define CLK_BUS_MCU_AUDIO_CODEC 21
|
||||
#define CLK_BUS_MCU_DSP_MSGBOX 22
|
||||
#define CLK_BUS_MCU_DSP_CFG 23
|
||||
#define CLK_BUS_MCU_NPU_HCLK 24
|
||||
#define CLK_BUS_MCU_NPU_ACLK 25
|
||||
#define CLK_MCU_TIMER0 26
|
||||
#define CLK_MCU_TIMER1 27
|
||||
#define CLK_MCU_TIMER2 28
|
||||
#define CLK_MCU_TIMER3 29
|
||||
#define CLK_MCU_TIMER4 30
|
||||
#define CLK_MCU_TIMER5 31
|
||||
#define CLK_BUS_MCU_TIMER 32
|
||||
#define CLK_BUS_MCU_DMA 33
|
||||
#define CLK_MCU_TZMA0 34
|
||||
#define CLK_MCU_TZMA1 35
|
||||
#define CLK_BUS_MCU_PUBSRAM 36
|
||||
#define CLK_MCU_MBUS_DMA 37
|
||||
#define CLK_MCU_MBUS 38
|
||||
#define CLK_MCU_RISCV 39
|
||||
#define CLK_BUS_MCU_RISCV_CFG 40
|
||||
#define CLK_BUS_MCU_RISCV_MSGBOX 41
|
||||
#define CLK_MCU_PWM0 42
|
||||
#define CLK_BUS_MCU_PWM0 43
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
|
||||
#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
|
||||
|
||||
#define RST_BUS_MCU_I2S0 0
|
||||
#define RST_BUS_MCU_I2S1 1
|
||||
#define RST_BUS_MCU_I2S2 2
|
||||
#define RST_BUS_MCU_I2S3 3
|
||||
#define RST_BUS_MCU_SPDIF 4
|
||||
#define RST_BUS_MCU_DMIC 5
|
||||
#define RST_BUS_MCU_AUDIO_CODEC 6
|
||||
#define RST_BUS_MCU_DSP_MSGBOX 7
|
||||
#define RST_BUS_MCU_DSP_CFG 8
|
||||
#define RST_BUS_MCU_NPU 9
|
||||
#define RST_BUS_MCU_TIMER 10
|
||||
#define RST_BUS_MCU_DSP_DEBUG 11
|
||||
#define RST_BUS_MCU_DSP 12
|
||||
#define RST_BUS_MCU_DMA 13
|
||||
#define RST_BUS_MCU_PUBSRAM 14
|
||||
#define RST_BUS_MCU_RISCV_CFG 15
|
||||
#define RST_BUS_MCU_RISCV_DEBUG 16
|
||||
#define RST_BUS_MCU_RISCV_CORE 17
|
||||
#define RST_BUS_MCU_RISCV_MSGBOX 18
|
||||
#define RST_BUS_MCU_PWM0 19
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */
|
||||
Loading…
Reference in New Issue