mirror of https://github.com/torvalds/linux.git
mtd: rawnand: cadence: Add support for NV-DDR interface mode
Add support for NV-DDR mode in the Cadence NAND controller driver. Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Niravkumar L Rabara
Miquel Raynal
parent
050553c683
commit
bf425fa103
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@ -199,6 +199,7 @@
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/* Common settings. */
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#define COMMON_SET 0x1008
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#define OPR_MODE_NVDDR BIT(0)
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/* 16 bit device connected to the NAND Flash interface. */
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#define COMMON_SET_DEVICE_16BIT BIT(8)
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@ -211,12 +212,20 @@
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#define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0)
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/* Timings configuration. */
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#define TOGGLE_TIMINGS_0 0x1014
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#define TOGGLE_TIMINGS_1 0x1018
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#define ASYNC_TOGGLE_TIMINGS 0x101c
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#define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24)
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#define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16)
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#define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8)
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#define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0)
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#define SYNC_TIMINGS 0x1020
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#define SYNC_TCKWR GENMASK(21, 16)
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#define SYNC_TWRCK GENMASK(13, 8)
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#define SYNC_TCAD GENMASK(5, 0)
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#define TIMINGS0 0x1024
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#define TIMINGS0_TADL GENMASK(31, 24)
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#define TIMINGS0_TCCS GENMASK(23, 16)
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@ -226,6 +235,7 @@
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#define TIMINGS1 0x1028
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#define TIMINGS1_TRHZ GENMASK(31, 24)
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#define TIMINGS1_TWB GENMASK(23, 16)
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#define TIMINGS1_TCWAW GENMASK(15, 8)
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#define TIMINGS1_TVDLY GENMASK(7, 0)
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#define TIMINGS2 0x102c
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@ -243,14 +253,23 @@
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/* Register controlling DQ related timing. */
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#define PHY_DQ_TIMING 0x2000
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#define PHY_DQ_TIMING_OE_END GENMASK(2, 0)
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#define PHY_DQ_TIMING_OE_START GENMASK(6, 4)
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#define PHY_DQ_TIMING_TSEL_END GENMASK(11, 8)
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#define PHY_DQ_TIMING_TSEL_START GENMASK(15, 12)
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/* Register controlling DSQ related timing. */
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#define PHY_DQS_TIMING 0x2004
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#define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0)
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#define PHY_DQS_TIMING_DQS_SEL_OE_START GENMASK(7, 4)
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#define PHY_DQS_TIMING_DQS_SEL_TSEL_END GENMASK(11, 8)
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#define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16)
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#define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
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/* Register controlling the gate and loopback control related timing. */
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#define PHY_GATE_LPBK_CTRL 0x2008
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#define PHY_GATE_LPBK_CTRL_GATE_CFG GENMASK(3, 0)
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#define PHY_GATE_LPBK_CTRL_GATE_CFG_CLOSE GENMASK(5, 4)
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#define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19)
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/* Register holds the control for the master DLL logic. */
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@ -260,6 +279,12 @@
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/* Register holds the control for the slave DLL logic. */
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#define PHY_DLL_SLAVE_CTRL 0x2010
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/* Register controls the DQS related timing. */
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#define PHY_IE_TIMING 0x2014
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#define PHY_IE_TIMING_DQS_IE_START GENMASK(10, 8)
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#define PHY_IE_TIMING_DQ_IE_START GENMASK(18, 16)
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#define PHY_IE_TIMING_IE_ALWAYS_ON BIT(20)
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/* This register handles the global control settings for the PHY. */
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#define PHY_CTRL 0x2080
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#define PHY_CTRL_SDR_DQS BIT(14)
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@ -375,15 +400,41 @@
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#define BCH_MAX_NUM_CORR_CAPS 8
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#define BCH_MAX_NUM_SECTOR_SIZES 2
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/* NVDDR mode specific parameters and register values based on cadence specs */
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#define NVDDR_PHY_RD_DELAY 29
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#define NVDDR_PHY_RD_DELAY_MAX 31
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#define NVDDR_GATE_CFG_OPT 14
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#define NVDDR_GATE_CFG_STD 7
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#define NVDDR_GATE_CFG_MAX 15
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#define NVDDR_DATA_SEL_OE_START 1
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#define NVDDR_DATA_SEL_OE_START_MAX 7
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#define NVDDR_DATA_SEL_OE_END 6
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#define NVDDR_DATA_SEL_OE_END_MIN 4
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#define NVDDR_DATA_SEL_OE_END_MAX 15
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#define NVDDR_RS_HIGH_WAIT_CNT 7
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#define NVDDR_RS_IDLE_CNT 7
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#define NVDDR_TCWAW_DELAY 250000
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#define NVDDR_TVDLY_DELAY 500000
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#define NVDDR_TOGGLE_TIMINGS_0 0x00000301
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#define NVDDR_TOGGLE_TIMINGS_1 0x0a060102
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#define NVDDR_ASYNC_TOGGLE_TIMINGS 0
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#define NVDDR_PHY_CTRL 0x00004000
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#define NVDDR_PHY_TSEL 0
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#define NVDDR_PHY_DLL_MASTER_CTRL 0x00140004
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#define NVDDR_PHY_DLL_SLAVE_CTRL 0x00003c3c
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struct cadence_nand_timings {
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u32 async_toggle_timings;
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u32 sync_timings;
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u32 timings0;
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u32 timings1;
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u32 timings2;
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u32 dll_phy_ctrl;
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u32 phy_ctrl;
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u32 phy_dq_timing;
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u32 phy_dqs_timing;
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u32 phy_gate_lpbk_ctrl;
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u32 phy_ie_timing;
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};
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/* Command DMA descriptor. */
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@ -2345,11 +2396,9 @@ static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
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return (trp_cnt + 1) * clk_period + trhoh_min - trea_max;
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}
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static int
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cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
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const struct nand_interface_config *conf)
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static int cadence_nand_setup_sdr_interface(struct nand_chip *chip,
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const struct nand_sdr_timings *sdr)
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{
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const struct nand_sdr_timings *sdr;
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struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
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struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
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struct cadence_nand_timings *t = &cdns_chip->timings;
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@ -2370,13 +2419,8 @@ cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
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u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0;
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u32 sampling_point;
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sdr = nand_get_sdr_timings(conf);
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if (IS_ERR(sdr))
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return PTR_ERR(sdr);
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memset(t, 0, sizeof(*t));
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/* Sampling point calculation. */
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if (cdns_ctrl->caps2.is_phy_type_dll)
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phony_dqs_mod = 2;
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else
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@ -2633,10 +2677,221 @@ cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
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PHY_DLL_MASTER_CTRL_BYPASS_MODE);
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dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0);
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}
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return 0;
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}
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static int
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cadence_nand_setup_nvddr_interface(struct nand_chip *chip,
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const struct nand_nvddr_timings *nvddr)
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{
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struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
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struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
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struct cadence_nand_timings *t = &cdns_chip->timings;
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u32 board_delay = cdns_ctrl->board_delay;
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u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
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cdns_ctrl->nf_clk_rate);
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u32 ddr_clk_ctrl_period = clk_period * 2;
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u32 if_skew = cdns_ctrl->caps1->if_skew;
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u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt;
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u32 twrck_cnt, tcad_cnt, tckwr_cnt = 0;
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u32 tfeat_cnt, trhz_cnt, tvdly_cnt, tcwaw_cnt;
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u32 trhw_cnt, twb_cnt, twhr_cnt;
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u32 oe_start, oe_end, oe_end_dqsd;
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u32 rd_del_sel = 0;
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u32 dqs_driven_by_device, dqs_toogle_by_device, gate_open_delay;
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u32 dll_phy_gate_open_delay, gate_close_delay, ie_start;
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u32 dll_phy_rd_delay;
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u32 reg;
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memset(t, 0, sizeof(*t));
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twrck_cnt = calc_cycl(nvddr->tWRCK_min, ddr_clk_ctrl_period);
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tcad_cnt = calc_cycl(nvddr->tCAD_min, ddr_clk_ctrl_period);
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reg = FIELD_PREP(SYNC_TWRCK, twrck_cnt);
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reg |= FIELD_PREP(SYNC_TCAD, tcad_cnt);
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t->sync_timings = reg;
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dev_dbg(cdns_ctrl->dev, "SYNC_TIMINGS_NVDDR\t%08x\n", reg);
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tadl_cnt = calc_cycl((nvddr->tADL_min + if_skew), ddr_clk_ctrl_period);
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tccs_cnt = calc_cycl((nvddr->tCCS_min + if_skew), ddr_clk_ctrl_period);
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twhr_cnt = calc_cycl((nvddr->tWHR_min + if_skew), ddr_clk_ctrl_period);
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trhw_cnt = calc_cycl((nvddr->tRHW_min + if_skew), ddr_clk_ctrl_period);
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reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt);
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reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt);
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reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt);
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reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt);
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t->timings0 = reg;
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dev_dbg(cdns_ctrl->dev, "TIMINGS0_NVDDR\t%08x\n", reg);
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twb_cnt = calc_cycl((nvddr->tWB_max + board_delay),
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ddr_clk_ctrl_period);
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/*
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* Because of the two stage syncflop the value must be increased by 3
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* first value is related with sync, second value is related
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* with output if delay.
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*/
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twb_cnt = twb_cnt + 3 + 5;
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tvdly_cnt = calc_cycl(NVDDR_TVDLY_DELAY + if_skew, ddr_clk_ctrl_period);
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tcwaw_cnt = calc_cycl(NVDDR_TCWAW_DELAY, ddr_clk_ctrl_period);
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trhz_cnt = 1;
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reg = FIELD_PREP(TIMINGS1_TWB, twb_cnt);
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reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt);
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reg |= FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt);
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reg |= FIELD_PREP(TIMINGS1_TCWAW, tcwaw_cnt);
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t->timings1 = reg;
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dev_dbg(cdns_ctrl->dev, "TIMINGS1_NVDDR\t%08x\n", reg);
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tfeat_cnt = calc_cycl(nvddr->tFEAT_max, ddr_clk_ctrl_period);
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if (tfeat_cnt < twb_cnt)
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tfeat_cnt = twb_cnt;
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tceh_cnt = calc_cycl(nvddr->tCEH_min, ddr_clk_ctrl_period);
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tcs_cnt = calc_cycl((nvddr->tCS_min + if_skew), ddr_clk_ctrl_period);
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reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt);
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reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt);
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reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt);
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t->timings2 = reg;
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dev_dbg(cdns_ctrl->dev, "TIMINGS2_NVDDR\t%08x\n", reg);
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reg = FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, NVDDR_RS_HIGH_WAIT_CNT);
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reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, NVDDR_RS_IDLE_CNT);
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t->dll_phy_ctrl = reg;
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dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_NVDDR\t%08x\n", reg);
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reg = PHY_CTRL_SDR_DQS;
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t->phy_ctrl = reg;
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dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_NVDDR\t%08x\n", reg);
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dqs_driven_by_device = (nvddr->tDQSD_max + board_delay) / 1000 +
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if_skew;
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dqs_toogle_by_device = (nvddr->tDQSCK_max + board_delay) / 1000 -
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if_skew;
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gate_open_delay = dqs_toogle_by_device / (clk_period / 1000);
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if (dqs_toogle_by_device > clk_period / 1000) {
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if (gate_open_delay > NVDDR_GATE_CFG_OPT)
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dll_phy_gate_open_delay = NVDDR_GATE_CFG_MAX;
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else
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dll_phy_gate_open_delay = gate_open_delay + 1;
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gate_close_delay = 0;
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} else {
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twrck_cnt = calc_cycl(dqs_driven_by_device * 1000, clk_period);
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dll_phy_gate_open_delay = 1;
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gate_close_delay = 0;
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reg = FIELD_PREP(SYNC_TCKWR, tckwr_cnt);
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reg |= FIELD_PREP(SYNC_TWRCK, twrck_cnt);
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reg |= FIELD_PREP(SYNC_TCAD, tcad_cnt);
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t->sync_timings = reg;
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dev_dbg(cdns_ctrl->dev, "SYNC_TIMINGS_NVDDR\t%08x\n", reg);
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}
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if (dll_phy_gate_open_delay > NVDDR_GATE_CFG_STD)
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ie_start = NVDDR_GATE_CFG_STD;
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else
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ie_start = dll_phy_gate_open_delay;
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dll_phy_rd_delay = ((nvddr->tDQSCK_max + board_delay) +
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(clk_period / 2)) / clk_period;
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if (dll_phy_rd_delay <= NVDDR_PHY_RD_DELAY)
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rd_del_sel = dll_phy_rd_delay + 2;
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else
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rd_del_sel = NVDDR_PHY_RD_DELAY_MAX;
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reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_GATE_CFG, dll_phy_gate_open_delay);
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reg |= FIELD_PREP(PHY_GATE_LPBK_CTRL_GATE_CFG_CLOSE, gate_close_delay);
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reg |= FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel);
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t->phy_gate_lpbk_ctrl = reg;
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dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_NVDDR\t%08x\n", reg);
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oe_end_dqsd = ((nvddr->tDQSD_max / 1000) / ((clk_period / 2) / 1000))
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+ NVDDR_DATA_SEL_OE_END_MIN;
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oe_end = (NVDDR_DATA_SEL_OE_END_MIN + oe_end_dqsd) / 2;
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if (oe_end > NVDDR_DATA_SEL_OE_END_MAX)
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oe_end = NVDDR_DATA_SEL_OE_END_MAX;
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oe_start = ((nvddr->tDQSHZ_max / 1000) / ((clk_period / 2) / 1000)) + 1;
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if (oe_start > NVDDR_DATA_SEL_OE_START_MAX)
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oe_start = NVDDR_DATA_SEL_OE_START_MAX;
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reg = FIELD_PREP(PHY_DQ_TIMING_OE_END, NVDDR_DATA_SEL_OE_END);
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reg |= FIELD_PREP(PHY_DQ_TIMING_OE_START, NVDDR_DATA_SEL_OE_START);
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reg |= FIELD_PREP(PHY_DQ_TIMING_TSEL_END, NVDDR_DATA_SEL_OE_END);
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reg |= FIELD_PREP(PHY_DQ_TIMING_TSEL_START, NVDDR_DATA_SEL_OE_START);
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t->phy_dq_timing = reg;
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dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_NVDDR\t%08x\n", reg);
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reg = FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, oe_end);
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reg |= FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_START, oe_start);
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reg |= FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_TSEL_END, oe_end);
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t->phy_dqs_timing = reg;
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dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_NVDDR\t%08x\n", reg);
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reg = FIELD_PREP(PHY_IE_TIMING_DQS_IE_START, ie_start);
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reg |= FIELD_PREP(PHY_IE_TIMING_DQ_IE_START, ie_start);
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reg |= FIELD_PREP(PHY_IE_TIMING_IE_ALWAYS_ON, 0);
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t->phy_ie_timing = reg;
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dev_dbg(cdns_ctrl->dev, "PHY_IE_TIMING_REG_NVDDR\t%08x\n", reg);
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reg = readl_relaxed(cdns_ctrl->reg + DLL_PHY_CTRL);
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reg &= ~(DLL_PHY_CTRL_DLL_RST_N |
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DLL_PHY_CTRL_EXTENDED_RD_MODE |
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DLL_PHY_CTRL_EXTENDED_WR_MODE);
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writel_relaxed(reg, cdns_ctrl->reg + DLL_PHY_CTRL);
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writel_relaxed(OPR_MODE_NVDDR, cdns_ctrl->reg + COMMON_SET);
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writel_relaxed(NVDDR_TOGGLE_TIMINGS_0,
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cdns_ctrl->reg + TOGGLE_TIMINGS_0);
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writel_relaxed(NVDDR_TOGGLE_TIMINGS_1,
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cdns_ctrl->reg + TOGGLE_TIMINGS_1);
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writel_relaxed(NVDDR_ASYNC_TOGGLE_TIMINGS,
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cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS);
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writel_relaxed(t->sync_timings, cdns_ctrl->reg + SYNC_TIMINGS);
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writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0);
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writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1);
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writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2);
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writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL);
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writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
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writel_relaxed(NVDDR_PHY_TSEL, cdns_ctrl->reg + PHY_TSEL);
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writel_relaxed(t->phy_dq_timing, cdns_ctrl->reg + PHY_DQ_TIMING);
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writel_relaxed(t->phy_dqs_timing, cdns_ctrl->reg + PHY_DQS_TIMING);
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writel_relaxed(t->phy_gate_lpbk_ctrl,
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cdns_ctrl->reg + PHY_GATE_LPBK_CTRL);
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writel_relaxed(NVDDR_PHY_DLL_MASTER_CTRL,
|
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cdns_ctrl->reg + PHY_DLL_MASTER_CTRL);
|
||||
writel_relaxed(NVDDR_PHY_DLL_SLAVE_CTRL,
|
||||
cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL);
|
||||
writel_relaxed(t->phy_ie_timing, cdns_ctrl->reg + PHY_IE_TIMING);
|
||||
writel_relaxed((reg | DLL_PHY_CTRL_DLL_RST_N),
|
||||
cdns_ctrl->reg + DLL_PHY_CTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (chipnr < 0)
|
||||
return ret;
|
||||
|
||||
if (nand_interface_is_sdr(conf)) {
|
||||
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
|
||||
|
||||
if (IS_ERR(sdr))
|
||||
return PTR_ERR(sdr);
|
||||
|
||||
ret = cadence_nand_setup_sdr_interface(chip, sdr);
|
||||
} else {
|
||||
const struct nand_nvddr_timings *nvddr = nand_get_nvddr_timings(conf);
|
||||
|
||||
if (IS_ERR(nvddr))
|
||||
return PTR_ERR(nvddr);
|
||||
|
||||
ret = cadence_nand_setup_nvddr_interface(chip, nvddr);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cadence_nand_attach_chip(struct nand_chip *chip)
|
||||
{
|
||||
struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
|
||||
|
|
|
|||
Loading…
Reference in New Issue