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Devicetree updates for v6.16: 

DT Bindings:
 - Convert all remaining interrupt-controller bindings to DT schema
 
 - Convert Rockchip CDN-DP and Freescale TCON, M4IF, TigerP, LDB, PPC
   PMC, imx-drm, and ftm-quaddec to DT schema
 
 - Add bindings for fsl,vf610-pit, fsl,ls1021a-wdt, sgx,vz89te,
   maxim,max30208, ti,lp8864, and fairphone,fp5-sndcard
 
 - Add top-level constraints for renesas,vsp1 and renesas,fcp
 
 - Add missing constraint in amlogic,pinctrl-a4 'group' nodes
 
 - Adjust the allowed properties for dwc3-xilinx, sony,imx219,
   pci-iommu, and renesas,dsi
 
 - Add EcoNet vendor prefix
 
 - Fix the reserved-memory.yaml in fsl,qman-fqd
 
 - Drop obsolete numa.txt and cpu-topology.txt which are schemas in
   dtschema now
 
 - Drop Renesas RZ/N1S bindings
 
 - Ensure Arm cpu nodes don't allow undocumented properties. Add all
   the properties which are in use and undocumented. Drop the Mediatek
   cpufreq binding which is not a binding, but just what DT properties
   the driver uses.
 
 - Add compatibles for Renesas RZ/G3E and RZ/V2N Mali Bifrost GPU
 
 - Update documentation on defining child nodes with separate schemas
 
 - Add bindings to PSCI MAINTAINERS entry
 
 DT core:
 - Add new functions to simplify driver handling of 'memory-region'
   properties. Users to be added next cycle.
 
 - Simplify of_dma_set_restricted_buffer() to use of_for_each_phandle()
 
 - Add missing unlock on error in unittest_data_add()
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Merge tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Convert all remaining interrupt-controller bindings to DT schema

   - Convert Rockchip CDN-DP and Freescale TCON, M4IF, TigerP, LDB, PPC
     PMC, imx-drm, and ftm-quaddec to DT schema

   - Add bindings for fsl,vf610-pit, fsl,ls1021a-wdt, sgx,vz89te,
     maxim,max30208, ti,lp8864, and fairphone,fp5-sndcard

   - Add top-level constraints for renesas,vsp1 and renesas,fcp

   - Add missing constraint in amlogic,pinctrl-a4 'group' nodes

   - Adjust the allowed properties for dwc3-xilinx, sony,imx219,
     pci-iommu, and renesas,dsi

   - Add EcoNet vendor prefix

   - Fix the reserved-memory.yaml in fsl,qman-fqd

   - Drop obsolete numa.txt and cpu-topology.txt which are schemas in
     dtschema now

   - Drop Renesas RZ/N1S bindings

   - Ensure Arm cpu nodes don't allow undocumented properties. Add all
     the properties which are in use and undocumented. Drop the Mediatek
     cpufreq binding which is not a binding, but just what DT properties
     the driver uses.

   - Add compatibles for Renesas RZ/G3E and RZ/V2N Mali Bifrost GPU

   - Update documentation on defining child nodes with separate schemas

   - Add bindings to PSCI MAINTAINERS entry

  DT core:

   - Add new functions to simplify driver handling of 'memory-region'
     properties. Users to be added next cycle.

   - Simplify of_dma_set_restricted_buffer() to use
     of_for_each_phandle()

   - Add missing unlock on error in unittest_data_add()"

* tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (87 commits)
  dt-bindings: timer: Add fsl,vf610-pit.yaml
  dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC
  ASoC: dt-bindings: qcom,sm8250: Add Fairphone 5 sound card
  dt-bindings: arm/cpus: Allow 2 power-domains entries
  dt-bindings: usb: dwc3-xilinx: allow dma-coherent
  media: dt-bindings: sony,imx219: Allow props from video-interface-devices
  dt-bindings: soundwire: qcom: Document v2.1.0 version of IP block
  dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1021a-wdt
  dt-bindings: pinctrl: amlogic,pinctrl-a4: Add missing constraint on allowed 'group' node properties
  dt-bindings: display: rockchip: Convert cdn-dp-rockchip.txt to yaml
  dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller
  dt-bindings: trivial-devices: Add VZ89TE to trivial
  media: dt-bindings: renesas,vsp1: add top-level constraints
  media: dt-bindings: renesas,fcp: add top-level constraints
  dt-bindings: trivial-devices: Add Maxim max30208
  dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml reference
  dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schema
  dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schema
  dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schema
  dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schema
  ...
This commit is contained in:
Linus Torvalds 2025-05-29 08:22:07 -07:00
parent 8ca154e491 89ab97de44
commit bf373e4c78
144 changed files with 4010 additions and 3574 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

232
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -10,9 +10,9 @@ maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |+
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
The device tree allows to describe the layout of CPUs in a system through the
"cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
properties for every cpu.
Bindings for CPU nodes follow the Devicetree Specification, available from:
@ -41,45 +41,40 @@ description: |+
properties:
reg:
maxItems: 1
description: |
Usage and definition depend on ARM architecture version and
configuration:
description: >
Usage and definition depend on ARM architecture version and configuration:
On uniprocessor ARM architectures previous to v7
this property is required and must be set to 0.
On uniprocessor ARM architectures previous to v7 this property is required
and must be set to 0.
On ARM 11 MPcore based systems this property is
required and matches the CPUID[11:0] register bits.
On ARM 11 MPcore based systems this property is required and matches the
CPUID[11:0] register bits.
Bits [11:0] in the reg cell must be set to
bits [11:0] in CPU ID register.
Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.
All other bits in the reg cell must be set to 0.
On 32-bit ARM v7 or later systems this property is
required and matches the CPU MPIDR[23:0] register
bits.
On 32-bit ARM v7 or later systems this property is required and matches
the CPU MPIDR[23:0] register bits.
Bits [23:0] in the reg cell must be set to
bits [23:0] in MPIDR.
Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR.
All other bits in the reg cell must be set to 0.
On ARM v8 64-bit systems this property is required
and matches the MPIDR_EL1 register affinity bits.
On ARM v8 64-bit systems this property is required and matches the
MPIDR_EL1 register affinity bits.
* If cpus node's #address-cells property is set to 2
The first reg cell bits [7:0] must be set to
bits [39:32] of MPIDR_EL1.
The first reg cell bits [7:0] must be set to bits [39:32] of
MPIDR_EL1.
The second reg cell bits [23:0] must be set to
bits [23:0] of MPIDR_EL1.
The second reg cell bits [23:0] must be set to bits [23:0] of
MPIDR_EL1.
* If cpus node's #address-cells property is set to 1
The reg cell bits [23:0] must be set to bits [23:0]
of MPIDR_EL1.
The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1.
All other bits in the reg cells must be set to 0.
@ -273,103 +268,122 @@ properties:
description:
The DT specification defines this as 64-bit always, but some 32-bit Arm
systems have used a 32-bit value which must be supported.
Required for systems that have an "enable-method"
property value of "spin-table".
cpu-idle-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).
description:
List of phandles to idle state nodes supported by this cpu (see
./idle-states.yaml).
capacity-dmips-mhz:
description:
u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
DMIPS/MHz, relative to highest capacity-dmips-mhz in the system.
cci-control-port: true
dynamic-power-coefficient:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
description: >
A u32 value that represents the running time dynamic power coefficient in
units of uW/MHz/V^2. The coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the CPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
The dynamic power consumption of the CPU is proportional to the square of
the Voltage (V) and the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
interconnects:
minItems: 1
maxItems: 3
nvmem-cells:
maxItems: 1
nvmem-cell-names:
const: speed_grade
performance-domains:
maxItems: 1
description:
List of phandles and performance domain specifiers, as defined by
bindings of the performance domain provider. See also
dvfs/performance-domain.yaml.
power-domains:
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider (see also ../power_domain.txt).
minItems: 1
maxItems: 2
power-domain-names:
description:
A list of power domain name strings sorted in the same order as the
power-domains property.
For PSCI based platforms, the name corresponding to the index of the PSCI
PM domain provider, must be "psci". For SCMI based platforms, the name
corresponding to the index of an SCMI performance domain provider, must be
"perf".
minItems: 1
maxItems: 2
items:
enum: [ psci, perf, cpr ]
resets:
maxItems: 1
arm-supply:
deprecated: true
description: Use 'cpu-supply' instead
cpu0-supply:
deprecated: true
description: Use 'cpu-supply' instead
mem-supply: true
proc-supply:
deprecated: true
description: Use 'cpu-supply' instead
sram-supply:
deprecated: true
description: Use 'mem-supply' instead
mediatek,cci:
$ref: /schemas/types.yaml#/definitions/phandle
description: Link to Mediatek Cache Coherent Interconnect
qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the SAW* node associated with this CPU.
Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
* arm/msm/qcom,saw2.txt
description:
Specifies the SAW node associated with this CPU.
qcom,acc:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the ACC* node associated with this CPU.
description:
Specifies the ACC node associated with this CPU.
Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
"qcom,msm8916-smp".
* arm/msm/qcom,kpss-acc.txt
qcom,freq-domain:
description: Specifies the QCom CPUFREQ HW associated with the CPU.
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
description: >
Specifies the syscon node controlling the cpu core power domains.
Optional for systems that have an "enable-method"
property value of "rockchip,rk3066-smp"
While optional, it is the preferred way to get access to
the cpu-core power-domains.
Optional for systems that have an "enable-method" property value of
"rockchip,rk3066-smp". While optional, it is the preferred way to get
access to the cpu-core power-domains.
secondary-boot-reg:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
description: >
Required for systems that have an "enable-method" property value of
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
This includes the following SoCs: |
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
This includes the following SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550,
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
The secondary-boot-reg property is a u32 value that specifies the
@ -378,22 +392,66 @@ properties:
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
if:
# If the enable-method property contains one of those values
properties:
enable-method:
contains:
enum:
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm-nsp-smp
# and if enable-method is present
required:
- enable-method
thermal-idle:
type: object
then:
required:
- secondary-boot-reg
allOf:
- $ref: /schemas/cpu.yaml#
- $ref: /schemas/opp/opp-v1.yaml#
- if:
# If the enable-method property contains one of those values
properties:
enable-method:
contains:
enum:
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm-nsp-smp
# and if enable-method is present
required:
- enable-method
then:
required:
- secondary-boot-reg
- if:
properties:
enable-method:
enum:
- spin-table
- renesas,r9a06g032-smp
required:
- enable-method
then:
required:
- cpu-release-addr
- if:
properties:
enable-method:
enum:
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- qcom,msm8226-smp
- qcom,msm8916-smp
required:
- enable-method
then:
required:
- qcom,acc
- qcom,saw
else:
if:
# 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use
# "spin-table" or "psci" enable-methods. Disallowing the properties for
# all other CPUs is the best we can do as there's not any way to
# distinguish these Qualcomm platforms.
not:
properties:
compatible:
const: arm,cortex-a53
then:
properties:
qcom,acc: false
qcom,saw: false
required:
- device_type
@ -403,7 +461,7 @@ required:
dependencies:
rockchip,pmu: [enable-method]
additionalProperties: true
unevaluatedProperties: false
examples:
- |

41
Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml Normal file
View File

@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module
description: collect the imx devices, which only have compatible and reg property
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx51-m4if
- fsl,imx51-tigerp
- fsl,imx51-aipstz
- fsl,imx53-aipstz
- fsl,imx7d-pcie-phy
- items:
- const: fsl,imx53-tigerp
- const: fsl,imx51-tigerp
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};

12
Documentation/devicetree/bindings/arm/freescale/m4if.txt
View File

@ -1,12 +0,0 @@
* Freescale Multi Master Multi Memory Interface (M4IF) module
Required properties:
- compatible : Should be "fsl,imx51-m4if"
- reg : Address and length of the register set for the device
Example:
m4if: m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};

12
Documentation/devicetree/bindings/arm/freescale/tigerp.txt
View File

@ -1,12 +0,0 @@
* Freescale Tigerp platform module
Required properties:
- compatible : Should be "fsl,imx51-tigerp"
- reg : Address and length of the register set for the device
Example:
tigerp: tigerp@83fa0000 {
compatible = "fsl,imx51-tigerp";
reg = <0x83fa0000 0x28>;
};

30
Documentation/devicetree/bindings/arm/psci.yaml
View File

@ -191,27 +191,27 @@ examples:
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
};
CPU1: cpu@1 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
};
idle-states {
CPU_PWRDN: cpu-power-down {
cpu_pwrdn: cpu-power-down {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0000001>;
entry-latency-us = <10>;
@ -222,7 +222,7 @@ examples:
domain-idle-states {
CLUSTER_RET: cluster-retention {
cluster_ret: cluster-retention {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x1000011>;
entry-latency-us = <500>;
@ -230,7 +230,7 @@ examples:
min-residency-us = <2000>;
};
CLUSTER_PWRDN: cluster-power-down {
cluster_pwrdn: cluster-power-down {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x1000031>;
entry-latency-us = <2000>;
@ -244,21 +244,21 @@ examples:
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
domain-idle-states = <&CPU_PWRDN>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&cpu_pwrdn>;
power-domains = <&cluster_pd>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
domain-idle-states = <&CPU_PWRDN>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&cpu_pwrdn>;
power-domains = <&cluster_pd>;
};
CLUSTER_PD: power-domain-cluster {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>;
};
};
...

36
Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml Normal file
View File

@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/counter/fsl,ftm-quaddec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FlexTimer Quadrature decoder counter
description:
Exposes a simple counter for the quadrature decoder mode.
maintainers:
- Frank Li <Frank.li@nxp.com>
properties:
compatible:
const: fsl,ftm-quaddec
reg:
maxItems: 1
big-endian: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
counter@29d0000 {
compatible = "fsl,ftm-quaddec";
reg = <0x29d0000 0x10000>;
big-endian;
};

18
Documentation/devicetree/bindings/counter/ftm-quaddec.txt
View File

@ -1,18 +0,0 @@
FlexTimer Quadrature decoder counter
This driver exposes a simple counter for the quadrature decoder mode.
Required properties:
- compatible: Must be "fsl,ftm-quaddec".
- reg: Must be set to the memory region of the flextimer.
Optional property:
- big-endian: Access the device registers in big-endian mode.
Example:
counter0: counter@29d0000 {
compatible = "fsl,ftm-quaddec";
reg = <0x0 0x29d0000 0x0 0x10000>;
big-endian;
status = "disabled";
};

553
Documentation/devicetree/bindings/cpu/cpu-topology.txt
View File

@ -1,553 +0,0 @@
===========================================
CPU topology binding description
===========================================
===========================================
1 - Introduction
===========================================
In a SMP system, the hierarchy of CPUs is defined through three entities that
are used to describe the layout of physical CPUs in the system:
- socket
- cluster
- core
- thread
The bottom hierarchy level sits at core or thread level depending on whether
symmetric multi-threading (SMT) is supported or not.
For instance in a system where CPUs support SMT, "cpu" nodes represent all
threads existing in the system and map to the hierarchy level "thread" above.
In systems where SMT is not supported "cpu" nodes represent all cores present
in the system and map to the hierarchy level "core" above.
CPU topology bindings allow one to associate cpu nodes with hierarchical groups
corresponding to the system hierarchy; syntactically they are defined as device
tree nodes.
Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
used for any other architecture as well.
The cpu nodes, as per bindings defined in [4], represent the devices that
correspond to physical CPUs and are to be mapped to the hierarchy levels.
A topology description containing phandles to cpu nodes that are not compliant
with bindings standardized in [4] is therefore considered invalid.
===========================================
2 - cpu-map node
===========================================
The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
child of the cpus node and provides a container where the actual topology
nodes are listed.
- cpu-map node
Usage: Optional - On SMP systems provide CPUs topology to the OS.
Uniprocessor systems do not require a topology
description and therefore should not define a
cpu-map node.
Description: The cpu-map node is just a container node where its
subnodes describe the CPU topology.
Node name must be "cpu-map".
The cpu-map node's parent node must be the cpus node.
The cpu-map node's child nodes can be:
- one or more cluster nodes or
- one or more socket nodes in a multi-socket system
Any other configuration is considered invalid.
The cpu-map node can only contain 4 types of child nodes:
- socket node
- cluster node
- core node
- thread node
whose bindings are described in paragraph 3.
The nodes describing the CPU topology (socket/cluster/core/thread) can
only be defined within the cpu-map node and every core/thread in the
system must be defined within the topology. Any other configuration is
invalid and therefore must be ignored.
===========================================
2.1 - cpu-map child nodes naming convention
===========================================
cpu-map child nodes must follow a naming convention where the node name
must be "socketN", "clusterN", "coreN", "threadN" depending on the node type
(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
which are siblings within a single common parent node must be given a unique and
sequential N value, starting from 0).
cpu-map child nodes which do not share a common parent node can have the same
name (ie same number N as other cpu-map child nodes at different device tree
levels) since name uniqueness will be guaranteed by the device tree hierarchy.
===========================================
3 - socket/cluster/core/thread node bindings
===========================================
Bindings for socket/cluster/cpu/thread nodes are defined as follows:
- socket node
Description: must be declared within a cpu-map node, one node
per physical socket in the system. A system can
contain single or multiple physical socket.
The association of sockets and NUMA nodes is beyond
the scope of this bindings, please refer [2] for
NUMA bindings.
This node is optional for a single socket system.
The socket node name must be "socketN" as described in 2.1 above.
A socket node can not be a leaf node.
A socket node's child nodes must be one or more cluster nodes.
Any other configuration is considered invalid.
- cluster node
Description: must be declared within a cpu-map node, one node
per cluster. A system can contain several layers of
clustering within a single physical socket and cluster
nodes can be contained in parent cluster nodes.
The cluster node name must be "clusterN" as described in 2.1 above.
A cluster node can not be a leaf node.
A cluster node's child nodes must be:
- one or more cluster nodes; or
- one or more core nodes
Any other configuration is considered invalid.
- core node
Description: must be declared in a cluster node, one node per core in
the cluster. If the system does not support SMT, core
nodes are leaf nodes, otherwise they become containers of
thread nodes.
The core node name must be "coreN" as described in 2.1 above.
A core node must be a leaf node if SMT is not supported.
Properties for core nodes that are leaf nodes:
- cpu
Usage: required
Value type: <phandle>
Definition: a phandle to the cpu node that corresponds to the
core node.
If a core node is not a leaf node (CPUs supporting SMT) a core node's
child nodes can be:
- one or more thread nodes
Any other configuration is considered invalid.
- thread node
Description: must be declared in a core node, one node per thread
in the core if the system supports SMT. Thread nodes are
always leaf nodes in the device tree.
The thread node name must be "threadN" as described in 2.1 above.
A thread node must be a leaf node.
A thread node must contain the following property:
- cpu
Usage: required
Value type: <phandle>
Definition: a phandle to the cpu node that corresponds to
the thread node.
===========================================
4 - Example dts
===========================================
Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single
physical socket):
cpus {
#size-cells = <0>;
#address-cells = <2>;
cpu-map {
socket0 {
cluster0 {
cluster0 {
core0 {
thread0 {
cpu = <&CPU0>;
};
thread1 {
cpu = <&CPU1>;
};
};
core1 {
thread0 {
cpu = <&CPU2>;
};
thread1 {
cpu = <&CPU3>;
};
};
};
cluster1 {
core0 {
thread0 {
cpu = <&CPU4>;
};
thread1 {
cpu = <&CPU5>;
};
};
core1 {
thread0 {
cpu = <&CPU6>;
};
thread1 {
cpu = <&CPU7>;
};
};
};
};
cluster1 {
cluster0 {
core0 {
thread0 {
cpu = <&CPU8>;
};
thread1 {
cpu = <&CPU9>;
};
};
core1 {
thread0 {
cpu = <&CPU10>;
};
thread1 {
cpu = <&CPU11>;
};
};
};
cluster1 {
core0 {
thread0 {
cpu = <&CPU12>;
};
thread1 {
cpu = <&CPU13>;
};
};
core1 {
thread0 {
cpu = <&CPU14>;
};
thread1 {
cpu = <&CPU15>;
};
};
};
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU4: cpu@10000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU5: cpu@10001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU6: cpu@10100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU7: cpu@10101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU8: cpu@100000000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU9: cpu@100000001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU10: cpu@100000100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU11: cpu@100000101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU12: cpu@100010000 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU13: cpu@100010001 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU14: cpu@100010100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
CPU15: cpu@100010101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x20000000>;
};
};
Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
};
};
Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
{
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,fu540g", "sifive,fu500";
model = "sifive,hifive-unleashed-a00";
...
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
socket0 {
cluster0 {
core0 {
cpu = <&CPU1>;
};
core1 {
cpu = <&CPU2>;
};
core2 {
cpu0 = <&CPU2>;
};
core3 {
cpu0 = <&CPU3>;
};
};
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "sifive,rocket0", "riscv";
reg = <0x1>;
}
CPU2: cpu@2 {
device_type = "cpu";
compatible = "sifive,rocket0", "riscv";
reg = <0x2>;
}
CPU3: cpu@3 {
device_type = "cpu";
compatible = "sifive,rocket0", "riscv";
reg = <0x3>;
}
CPU4: cpu@4 {
device_type = "cpu";
compatible = "sifive,rocket0", "riscv";
reg = <0x4>;
}
}
};
===============================================================================
[1] ARM Linux kernel documentation
Documentation/devicetree/bindings/arm/cpus.yaml
[2] Devicetree NUMA binding description
Documentation/devicetree/bindings/numa.txt
[3] RISC-V Linux kernel documentation
Documentation/devicetree/bindings/riscv/cpus.yaml
[4] https://www.devicetree.org/specifications/

250
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
View File

@ -1,250 +0,0 @@
Binding for MediaTek's CPUFreq driver
=====================================
Required properties:
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
- clock-names: Should contain the following:
"cpu" - The multiplexer for clock input of CPU cluster.
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
source (usually MAINPLL) when the original CPU PLL is under
transition and not stable yet.
Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
generic clock consumer properties.
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
for detail.
- proc-supply: Regulator for Vproc of CPU cluster.
Optional properties:
- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
needs to do "voltage tracking" to step by step scale up/down Vproc and
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- mediatek,cci:
Used to confirm the link status between cpufreq and mediatek cci. Because
cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
To prevent the issue of high frequency and low voltage, we need to use this
property to make sure mediatek cci is ready.
For details of mediatek cci, please refer to
Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
Example 1 (MT7623 SoC):
cpu_opp_table: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-598000000 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <1050000>;
};
opp-747500000 {
opp-hz = /bits/ 64 <747500000>;
opp-microvolt = <1050000>;
};
opp-1040000000 {
opp-hz = /bits/ 64 <1040000000>;
opp-microvolt = <1150000>;
};
opp-1196000000 {
opp-hz = /bits/ 64 <1196000000>;
opp-microvolt = <1200000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1300000>;
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&infracfg CLK_INFRA_CPUSEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
};
Example 2 (MT8173 SoC):
cpu_opp_table_a: opp_table_a {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
opp-hz = /bits/ 64 <507000000>;
opp-microvolt = <859000>;
};
opp-702000000 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <908000>;
};
opp-1001000000 {
opp-hz = /bits/ 64 <1001000000>;
opp-microvolt = <983000>;
};
opp-1105000000 {
opp-hz = /bits/ 64 <1105000000>;
opp-microvolt = <1009000>;
};
opp-1183000000 {
opp-hz = /bits/ 64 <1183000000>;
opp-microvolt = <1028000>;
};
opp-1404000000 {
opp-hz = /bits/ 64 <1404000000>;
opp-microvolt = <1083000>;
};
opp-1508000000 {
opp-hz = /bits/ 64 <1508000000>;
opp-microvolt = <1109000>;
};
opp-1573000000 {
opp-hz = /bits/ 64 <1573000000>;
opp-microvolt = <1125000>;
};
};
cpu_opp_table_b: opp_table_b {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
opp-hz = /bits/ 64 <507000000>;
opp-microvolt = <828000>;
};
opp-702000000 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <867000>;
};
opp-1001000000 {
opp-hz = /bits/ 64 <1001000000>;
opp-microvolt = <927000>;
};
opp-1209000000 {
opp-hz = /bits/ 64 <1209000000>;
opp-microvolt = <968000>;
};
opp-1404000000 {
opp-hz = /bits/ 64 <1007000000>;
opp-microvolt = <1028000>;
};
opp-1612000000 {
opp-hz = /bits/ 64 <1612000000>;
opp-microvolt = <1049000>;
};
opp-1807000000 {
opp-hz = /bits/ 64 <1807000000>;
opp-microvolt = <1089000>;
};
opp-1989000000 {
opp-hz = /bits/ 64 <1989000000>;
opp-microvolt = <1125000>;
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA53SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_a>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA53SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_a>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
};
&cpu0 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu1 {
proc-supply = <&mt6397_vpca15_reg>;
};
&cpu2 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};
&cpu3 {
proc-supply = <&da9211_vcpu_reg>;
sram-supply = <&mt6397_vsramca7_reg>;
};

67
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
View File

@ -128,7 +128,7 @@ required:
- power-domains
- ports
additionalProperties: false
unevaluatedProperties: false
examples:
- |
@ -180,4 +180,69 @@ examples:
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
dsi1: dsi@10860000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
reg = <0x10860000 0x20000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "seq0", "seq1", "vin1", "rcv",
"ferr", "ppi", "debug";
clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
<&cpg R9A07G044_MIPI_DSI_ARESET_N>,
<&cpg R9A07G044_MIPI_DSI_PRESET_N>;
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
panel@0 {
compatible = "rocktech,jh057n00900";
reg = <0>;
vcc-supply = <&reg_2v8_p>;
iovcc-supply = <&reg_1v8_p>;
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&du_out_dsi1>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&panel_in>;
};
};
};
};
...

17
Documentation/devicetree/bindings/display/fsl,tcon.txt
View File

@ -1,17 +0,0 @@
Device Tree bindings for Freescale TCON Driver
Required properties:
- compatible: Should be one of
* "fsl,vf610-tcon".
- reg: Address and length of the register set for tcon.
- clocks: From common clock binding: handle to tcon ipg clock.
- clock-names: From common clock binding: Shall be "ipg".
Examples:
timing-controller@4003d000 {
compatible = "fsl,vf610-tcon";
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
};

43
Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml Normal file
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@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/fsl,vf610-tcon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale TCON
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,vf610-tcon
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: ipg
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/vf610-clock.h>
timing-controller@4003d000 {
compatible = "fsl,vf610-tcon";
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
};

36
Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml Normal file
View File

@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX DRM master device
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
The freescale i.MX DRM master device is a virtual device needed to list all
IPU or other display interface nodes that comprise the graphics subsystem.
properties:
compatible:
const: fsl,imx-display-subsystem
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Should contain a list of phandles pointing to camera
sensor interface ports of IPU devices.
required:
- compatible
additionalProperties: false
examples:
- |
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>;
};

74
Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml Normal file
View File

@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Parallel display support
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx-parallel-display
interface-pix-fmt:
$ref: /schemas/types.yaml#/definitions/string
enum:
- rgb24
- rgb565
- bgr666
- lvds666
ddc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle describing the i2c bus handling the display data channel
'#address-cells':
const: 1
'#size-cells':
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: input port connected to the IPU display interface
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: output port connected to a panel
required:
- compatible
additionalProperties: false
examples:
- |
display {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&panel_in>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX IPUv3
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx51-ipu
- fsl,imx53-ipu
- fsl,imx6q-ipu
- items:
- const: fsl,imx6qp-ipu
- const: fsl,imx6q-ipu
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
clocks:
maxItems: 3
clock-names:
items:
- const: bus
- const: di0
- const: di1
resets:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
fsl,prg:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to prg node associated with this IPU instance
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI0
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI1
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DI0
port@3:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DI1
required:
- compatible
- reg
- interrupts
- resets
additionalProperties: false
examples:
- |
display-controller@18000000 {
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11 10>;
resets = <&src 2>;
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&display_in>;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale LVDS Display Bridge (ldb)
description:
The LVDS Display Bridge device tree node contains up to two lvds-channel
nodes describing each of the two LVDS encoder channels of the bridge.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx53-ldb
- items:
- enum:
- fsl,imx6q-ldb
- const: fsl,imx53-ldb
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle points to the iomuxc-gpr region containing the LVDS
control register.
clocks:
minItems: 6
maxItems: 8
clock-names:
oneOf:
- items:
- const: di0_pll
- const: di1_pll
- const: di0_sel
- const: di1_sel
- const: di0
- const: di1
- items:
- const: di0_pll
- const: di1_pll
- const: di0_sel
- const: di1_sel
- const: di2_sel
- const: di3_sel
- const: di0
- const: di1
fsl,dual-channel:
$ref: /schemas/types.yaml#/definitions/flag
description:
if it exists, only LVDS channel 0 should
be configured - one input will be distributed on both outputs in dual
channel mode
patternProperties:
'^lvds-channel@[0-1]$':
type: object
description:
Each LVDS Channel has to contain either an of graph link to a panel device node
or a display-timings node that describes the video timings for the connected
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
properties:
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
display-timings:
$ref: /schemas/display/panel/display-timings.yaml#
fsl,data-mapping:
enum:
- spwg
- jeida
fsl,data-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: should be <18> or <24>
enum:
- 18
- 24
fsl,panel:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to lcd panel
patternProperties:
'^port@[0-4]$':
$ref: /schemas/graph.yaml#/properties/port
description:
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
limitations, only one input port (port@[0,1]) can be used for each channel
(lvds-channel@[0,1], respectively).
On i.MX6, there should be four input ports (port@[0-3]) that correspond
to the four LVDS multiplexer inputs.
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
to a panel input port. Optionally, the output port can be left out if
display-timings are used instead.
additionalProperties: false
required:
- compatible
- gpr
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
ldb@53fa8008 {
compatible = "fsl,imx53-ldb";
reg = <0x53fa8008 0x4>;
#address-cells = <1>;
#size-cells = <0>;
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
/* Using an of-graph endpoint link to connect the panel */
lvds-channel@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&panel_in>;
};
};
};
/* Using display-timings and fsl,data-mapping/width instead */
lvds-channel@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {/* ... */
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX PRE (Prefetch Resolve Engine)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx6qp-pre
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: axi
fsl,iram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle pointing to the mmio-sram device node, that should be
used for the PRE SRAM double buffer.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE0>;
clock-names = "axi";
fsl,iram = <&ocram2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX PRG (Prefetch Resolve Gasket)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx6qp-prg
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: ipg
- const: axi
fsl,pres:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
phandles to the PRE units attached to this PRG, with the fixed
PRE as the first entry and the muxable PREs following.
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
prg@21cc000 {
compatible = "fsl,imx6qp-prg";
reg = <0x021cc000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
};

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Freescale i.MX DRM master device
================================
The freescale i.MX DRM master device is a virtual device needed to list all
IPU or other display interface nodes that comprise the graphics subsystem.
Required properties:
- compatible: Should be "fsl,imx-display-subsystem"
- ports: Should contain a list of phandles pointing to display interface ports
of IPU devices
example:
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>;
};
Freescale i.MX IPUv3
====================
Required properties:
- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
- imx51
- imx53
- imx6q
- imx6qp
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain sync interrupt and error interrupt,
in this order.
- resets: phandle pointing to the system reset controller and
reset line index, see reset/fsl,imx-src.txt for details
Additional required properties for fsl,imx6qp-ipu:
- fsl,prg: phandle to prg node associated with this IPU instance
Optional properties:
- port@[0-3]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Ports 0 and 1 should correspond to CSI0 and CSI1,
ports 2 and 3 should correspond to DI0 and DI1, respectively.
example:
ipu: ipu@18000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
resets = <&src 2>;
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp0: endpoint {
remote-endpoint = <&display_in>;
};
};
};
Freescale i.MX PRE (Prefetch Resolve Engine)
============================================
Required properties:
- compatible: should be "fsl,imx6qp-pre"
- reg: should be register base and length as documented in the
datasheet
- clocks : phandle to the PRE axi clock input, as described
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
- clock-names: should be "axi"
- interrupts: should contain the PRE interrupt
- fsl,iram: phandle pointing to the mmio-sram device node, that should be
used for the PRE SRAM double buffer.
example:
pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE0>;
clock-names = "axi";
fsl,iram = <&ocram2>;
};
Freescale i.MX PRG (Prefetch Resolve Gasket)
============================================
Required properties:
- compatible: should be "fsl,imx6qp-prg"
- reg: should be register base and length as documented in the
datasheet
- clocks : phandles to the PRG ipg and axi clock inputs, as described
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
- clock-names: should be "ipg" and "axi"
- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
PRE as the first entry and the muxable PREs following.
example:
prg@21cc000 {
compatible = "fsl,imx6qp-prg";
reg = <0x021cc000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
<&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
};
Parallel display support
========================
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
- interface-pix-fmt: How this display is connected to the
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
and "lvds666".
- ddc: phandle describing the i2c bus handling the display data
channel
- port@[0-1]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Port 0 is the input port connected to the IPU display interface,
port 1 is the output port connected to a panel.
example:
disp0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
port@0 {
reg = <0>;
display_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel {
...
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};

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Device-Tree bindings for LVDS Display Bridge (ldb)
LVDS Display Bridge
===================
The LVDS Display Bridge device tree node contains up to two lvds-channel
nodes describing each of the two LVDS encoder channels of the bridge.
Required properties:
- #address-cells : should be <1>
- #size-cells : should be <0>
- compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
Both LDB versions are similar, but i.MX6 has an additional
multiplexer in the front to select any of the four IPU display
interfaces as input for each LVDS channel.
- gpr : should be <&gpr> on i.MX53 and i.MX6q.
The phandle points to the iomuxc-gpr region containing the LVDS
control register.
- clocks, clock-names : phandles to the LDB divider and selector clocks and to
the display interface selector clocks, as described in
Documentation/devicetree/bindings/clock/clock-bindings.txt
The following clocks are expected on i.MX53:
"di0_pll" - LDB LVDS channel 0 mux
"di1_pll" - LDB LVDS channel 1 mux
"di0" - LDB LVDS channel 0 gate
"di1" - LDB LVDS channel 1 gate
"di0_sel" - IPU1 DI0 mux
"di1_sel" - IPU1 DI1 mux
On i.MX6q the following additional clocks are needed:
"di2_sel" - IPU2 DI0 mux
"di3_sel" - IPU2 DI1 mux
The needed clock numbers for each are documented in
Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
Optional properties:
- pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
- pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
not used on i.MX6q
- fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
be configured - one input will be distributed on both outputs in dual
channel mode
LVDS Channel
============
Each LVDS Channel has to contain either an of graph link to a panel device node
or a display-timings node that describes the video timings for the connected
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
Required properties:
- reg : should be <0> or <1>
- port: Input and output port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/graph.txt.
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
limitations, only one input port (port@[0,1]) can be used for each channel
(lvds-channel@[0,1], respectively).
On i.MX6, there should be four input ports (port@[0-3]) that correspond
to the four LVDS multiplexer inputs.
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
to a panel input port. Optionally, the output port can be left out if
display-timings are used instead.
Optional properties (required if display-timings are used):
- display-timings : A node that describes the display timings as defined in
Documentation/devicetree/bindings/display/panel/display-timing.txt.
- fsl,data-mapping : should be "spwg" or "jeida"
This describes how the color bits are laid out in the
serialized LVDS signal.
- fsl,data-width : should be <18> or <24>
example:
gpr: iomuxc-gpr@53fa8000 {
/* ... */
};
ldb: ldb@53fa8008 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ldb";
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
/* Using an of-graph endpoint link to connect the panel */
lvds-channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
};
port@2 {
reg = <2>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
/* Using display-timings and fsl,data-mapping/width instead */
lvds-channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {
/* ... */
};
port@1 {
reg = <1>;
lvds1_in: endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
};
};
};
panel: lvds-panel {
/* ... */
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};

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Rockchip RK3399 specific extensions to the cdn Display Port
================================
Required properties:
- compatible: must be "rockchip,rk3399-cdn-dp"
- reg: physical base address of the controller and length
- clocks: from common clock binding: handle to dp clock.
- clock-names: from common clock binding:
Required elements: "core-clk" "pclk" "spdif" "grf"
- resets : a list of phandle + reset specifier pairs
- reset-names : string of reset names
Required elements: "apb", "core", "dptx", "spdif"
- power-domains : power-domain property defined with a phandle
to respective power domain.
- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
- rockchip,grf: this soc should set GRF regs, so need get grf here.
- ports: contain a port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
contained 2 endpoints, connecting to the output of vop.
- phys: from general PHY binding: the phandle for the PHY device.
- extcon: extcon specifier for the Power Delivery
- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
-------------------------------------------------------------------------------
Example:
cdn_dp: dp@fec00000 {
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>;
reset-names = "spdif";
extcon = <&fusb0>, <&fusb1>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
dp_in: port {
#address-cells = <1>;
#size-cells = <0>;
dp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dp>;
};
dp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dp>;
};
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3399 specific extensions to the CDN Display Port
maintainers:
- Andy Yan <andy.yan@rock-chip.com>
- Heiko Stuebner <heiko@sntech.de>
- Sandy Huang <hjc@rock-chips.com>
allOf:
- $ref: /schemas/sound/dai-common.yaml#
properties:
compatible:
items:
- const: rockchip,rk3399-cdn-dp
reg:
maxItems: 1
clocks:
items:
- description: DP core work clock
- description: APB clock
- description: SPDIF interface clock
- description: GRF clock
clock-names:
items:
- const: core-clk
- const: pclk
- const: spdif
- const: grf
extcon:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
items:
- description: Extcon device providing the cable state for DP PHY device 0
- description: Extcon device providing the cable state for DP PHY device 1
description:
List of phandle to the extcon device providing the cable state for the DP PHY.
interrupts:
maxItems: 1
phys:
minItems: 1
items:
- description: DP output to the DP PHY device 0
- description: DP output to the DP PHY device 1
description:
RK3399 have two DP-USB PHY, specifying one PHY which want to use, or
specify two PHYs here to let the driver determine which PHY to use.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input of the CDN DP
properties:
endpoint@0:
description: Connection to the VOPB
endpoint@1:
description: Connection to the VOPL
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output of the CDN DP
required:
- port@0
- port@1
power-domains:
maxItems: 1
resets:
maxItems: 4
reset-names:
items:
- const: spdif
- const: dptx
- const: apb
- const: core
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to GRF register to control HPD.
"#sound-dai-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- phys
- ports
- resets
- reset-names
- rockchip,grf
- "#sound-dai-cells"
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3399-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
dp@fec00000 {
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>,
<&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
<&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
reset-names = "spdif", "dptx", "apb", "core";
rockchip,grf = <&grf>;
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
dp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dp>;
};
dp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dp>;
};
};
dp_out: port@1 {
reg = <1>;
};
};
};
};

15
Documentation/devicetree/bindings/example-schema.yaml
View File

@ -178,7 +178,9 @@ properties:
description: Child nodes are just another property from a json-schema
perspective.
type: object # DT nodes are json objects
# Child nodes also need additionalProperties or unevaluatedProperties
# Child nodes also need additionalProperties or unevaluatedProperties, where
# 'false' should be used in most cases (see 'child-node-with-own-schema'
# below).
additionalProperties: false
properties:
vendor,a-child-node-property:
@ -189,6 +191,17 @@ properties:
required:
- vendor,a-child-node-property
child-node-with-own-schema:
description: |
Child node with their own compatible and device schema which ends in
'additionalProperties: false' or 'unevaluatedProperties: false' can
mention only the compatible and use here 'additionalProperties: true'.
type: object
additionalProperties: true
properties:
compatible:
const: vendor,sub-device
# Describe the relationship between different properties
dependencies:
# 'vendor,bool-property' is only allowed when 'vendor,string-array-property'

4
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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@ -25,6 +25,8 @@ properties:
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g047-mali
- renesas,r9a09g056-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
@ -145,6 +147,8 @@ allOf:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g047-mali
- renesas,r9a09g056-mali
- renesas,r9a09g057-mali
then:
properties:

37
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@ -1,37 +0,0 @@
TB10x Top Level Interrupt Controller
====================================
The Abilis TB10x SOC contains a custom interrupt controller. It performs
one-to-one mapping of external interrupt sources to CPU interrupts and
provides support for reconfigurable trigger modes.
Required properties
-------------------
- compatible: Should be "abilis,tb10x-ictl"
- reg: specifies physical base address and size of register range.
- interrupt-congroller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
source connected to this controller. The value shall be 2.
- interrupts: Specifies the list of interrupt lines which are handled by
the interrupt controller in the parent controller's notation. Interrupts
are mapped one-to-one to parent interrupts.
Example
-------
intc: interrupt-controller { /* Parent interrupt controller */
interrupt-controller;
#interrupt-cells = <1>; /* For example below */
/* ... */
};
tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
compatible = "abilis,tb10x-ictl";
reg = <0x2000 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31>;
};

54
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/abilis,tb10x-ictl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TB10x Top Level Interrupt Controller
maintainers:
- Christian Ruppert <christian.ruppert@abilis.com>
description:
The Abilis TB10x SOC contains a custom interrupt controller. It performs
one-to-one mapping of external interrupt sources to CPU interrupts and
provides support for reconfigurable trigger modes.
properties:
compatible:
const: abilis,tb10x-ictl
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: A one-to-one mapping of external interrupt sources to parent
interrupts.
minItems: 1
maxItems: 32
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@2000 {
compatible = "abilis,tb10x-ictl";
reg = <0x2000 0x20>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <5>, <6>, <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>,
<15>, <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>,
<24>, <25>, <26>, <27>, <28>, <29>, <30>, <31>;
};

25
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@ -1,25 +0,0 @@
Alpine MSIX controller
See arm,gic-v3.txt for SPI and MSI definitions.
Required properties:
- compatible: should be "al,alpine-msix"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- msi-controller: identifies the node as an PCI Message Signaled Interrupt
controller
- al,msi-base-spi: SPI base of the MSI frame
- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
Example:
msix: msix {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-parent = <&gic>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;
};

49
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Alpine MSIX controller
maintainers:
- Antoine Tenart <atenart@kernel.org>
properties:
compatible:
const: al,alpine-msix
reg:
maxItems: 1
interrupt-parent: true
msi-controller: true
al,msi-base-spi:
description: SPI base of the MSI frame
$ref: /schemas/types.yaml#/definitions/uint32
al,msi-num-spis:
description: number of SPIs assigned to the MSI frame, relative to SPI0
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- msi-controller
- al,msi-base-spi
- al,msi-num-spis
additionalProperties: false
examples:
- |
msi-controller@fbe00000 {
compatible = "al,alpine-msix";
reg = <0xfbe00000 0x100000>;
interrupt-parent = <&gic>;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;
};

2
Documentation/devicetree/bindings/pci/altr,msi-controller.yaml → Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml
View File

@ -2,7 +2,7 @@
# Copyright (C) 2015, 2024, Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/altr,msi-controller.yaml#
$id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera PCIe MSI controller

27
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@ -1,27 +0,0 @@
Amazon's Annapurna Labs Fabric Interrupt Controller
Required properties:
- compatible: should be "amazon,al-fic"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells : must be 2. Specifies the number of cells needed to encode
an interrupt source. Supported trigger types are low-to-high edge
triggered and active high level-sensitive.
- interrupts: describes which input line in the interrupt parent, this
fic's output is connected to. This field property depends on the parent's
binding
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
amazon_fic: interrupt-controller@fd8a8500 {
compatible = "amazon,al-fic";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xfd8a8500 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;
};

46
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/amazon,al-fic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amazon Annapurna Labs Fabric Interrupt Controller
maintainers:
- Talel Shenhar <talel@amazon.com>
properties:
compatible:
const: amazon,al-fic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@fd8a8500 {
compatible = "amazon,al-fic";
reg = <0xfd8a8500 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;
};

36
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@ -1,36 +0,0 @@
* ARM Nested Vector Interrupt Controller (NVIC)
The NVIC provides an interrupt controller that is tightly coupled to
Cortex-M based processor cores. The NVIC implemented on different SoCs
vary in the number of interrupts and priority bits per interrupt.
Main node required properties:
- compatible : should be one of:
"arm,v6m-nvic"
"arm,v7m-nvic"
"arm,v8m-nvic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
The 1st cell contains the interrupt number for the interrupt type.
The 2nd cell is the priority of the interrupt.
- reg : Specifies base physical address(s) and size of the NVIC registers.
This is at a fixed address (0xe000e100) and size (0xc00).
- arm,num-irq-priority-bits: The number of priority bits implemented by the
given SoC
Example:
intc: interrupt-controller@e000e100 {
compatible = "arm,v7m-nvic";
#interrupt-cells = <2>;
#address-cells = <1>;
interrupt-controller;
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <4>;
};

61
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Nested Vector Interrupt Controller (NVIC)
maintainers:
- Rob Herring <robh@kernel.org>
description:
The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
based processor cores. The NVIC implemented on different SoCs vary in the
number of interrupts and priority bits per interrupt.
properties:
compatible:
enum:
- arm,v6m-nvic
- arm,v7m-nvic
- arm,v8m-nvic
reg:
maxItems: 1
'#address-cells':
const: 0
interrupt-controller: true
'#interrupt-cells':
const: 2
description: |
Number of cells to encode an interrupt source:
first = interrupt number, second = priority.
arm,num-irq-priority-bits:
description: Number of priority bits implemented by the SoC
minimum: 1
maximum: 8
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- arm,num-irq-priority-bits
additionalProperties: false
examples:
- |
interrupt-controller@e000e100 {
compatible = "arm,v7m-nvic";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <4>;
};

38
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@ -1,38 +0,0 @@
* ARM Versatile FPGA interrupt controller
One or more FPGA IRQ controllers can be synthesized in an ARM reference board
such as the Integrator or Versatile family. The output of these different
controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.
Required properties:
- compatible: "arm,versatile-fpga-irq"
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
as the FPGA IRQ controller has no configuration options for interrupt
sources. The cell is a u32 and defines the interrupt number.
- reg: The register bank for the FPGA interrupt controller.
- clear-mask: a u32 number representing the mask written to clear all IRQs
on the controller at boot for example.
- valid-mask: a u32 number representing a bit mask determining which of
the interrupts are valid. Unconnected/unused lines are set to 0, and
the system till not make it possible for devices to request these
interrupts.
The "oxsemi,ox810se-rps-irq" compatible is deprecated.
Example:
pic: pic@14000000 {
compatible = "arm,versatile-fpga-irq";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x14000000 0x100>;
clear-mask = <0xffffffff>;
valid-mask = <0x003fffff>;
};
Optional properties:
- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
output is simply connected to the input of another IRQ controller,
then the parent IRQ shall be specified in this property.

61
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile FPGA IRQ Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
One or more FPGA IRQ controllers can be synthesized in an ARM reference board
such as the Integrator or Versatile family. The output of these different
controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.
properties:
compatible:
const: arm,versatile-fpga-irq
interrupt-controller: true
'#interrupt-cells':
const: 1
reg:
maxItems: 1
clear-mask:
description: A mask written to clear all IRQs on the controller at boot.
$ref: /schemas/types.yaml#/definitions/uint32
valid-mask:
description:
A bit mask determining which interrupts are valid; unused lines are set to 0.
$ref: /schemas/types.yaml#/definitions/uint32
interrupts:
maxItems: 1
additionalProperties: false
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
- reg
- clear-mask
- valid-mask
examples:
- |
interrupt-controller@14000000 {
compatible = "arm,versatile-fpga-irq";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x14000000 0x100>;
clear-mask = <0xffffffff>;
valid-mask = <0x003fffff>;
};

25
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
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@ -1,25 +0,0 @@
Device tree configuration for the I2C Interrupt Controller on the AST24XX and
AST25XX SoCs.
Required Properties:
- #address-cells : should be 1
- #size-cells : should be 1
- #interrupt-cells : should be 1
- compatible : should be "aspeed,ast2400-i2c-ic"
or "aspeed,ast2500-i2c-ic"
- reg : address start and range of controller
- interrupts : interrupt number
- interrupt-controller : denotes that the controller receives and fires
new interrupts for child busses
Example:
i2c_ic: interrupt-controller@0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
compatible = "aspeed,ast2400-i2c-ic";
reg = <0x0 0x40>;
interrupts = <12>;
interrupt-controller;
};

46
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-i2c-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed I2C Interrupt Controller (AST24XX/AST25XX)
maintainers:
- Ryan Chen <ryan_chen@aspeedtech.com>
properties:
compatible:
enum:
- aspeed,ast2400-i2c-ic
- aspeed,ast2500-i2c-ic
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- '#interrupt-cells'
- interrupts
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller@0 {
compatible = "aspeed,ast2400-i2c-ic";
reg = <0x0 0x40>;
#interrupt-cells = <1>;
interrupts = <12>;
interrupt-controller;
};

48
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@ -0,0 +1,48 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 Eddie James
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed AST25XX and AST26XX SCU Interrupt Controller
maintainers:
- Eddie James <eajames@linux.ibm.com>
properties:
compatible:
enum:
- aspeed,ast2500-scu-ic
- aspeed,ast2600-scu-ic0
- aspeed,ast2600-scu-ic1
reg:
maxItems: 1
'#interrupt-cells':
const: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- compatible
- reg
- '#interrupt-cells'
- interrupts
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller@18 {
compatible = "aspeed,ast2500-scu-ic";
reg = <0x18 0x4>;
#interrupt-cells = <1>;
interrupts = <21>;
interrupt-controller;
};

23
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt
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@ -1,23 +0,0 @@
Aspeed AST25XX and AST26XX SCU Interrupt Controller
Required Properties:
- #interrupt-cells : must be 1
- compatible : must be "aspeed,ast2500-scu-ic",
"aspeed,ast2600-scu-ic0" or
"aspeed,ast2600-scu-ic1"
- interrupts : interrupt from the parent controller
- interrupt-controller : indicates that the controller receives and
fires new interrupts for child busses
Example:
syscon@1e6e2000 {
ranges = <0 0x1e6e2000 0x1a8>;
scu_ic: interrupt-controller@18 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2500-scu-ic";
interrupts = <21>;
interrupt-controller;
};
};

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@ -1,131 +0,0 @@
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
The BCM2835 contains a custom top-level interrupt controller, which supports
72 interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence naming of this binding.
The BCM2836 contains the same interrupt controller with the same
interrupts, but the per-CPU interrupt controller is the root, and an
interrupt there indicates that the ARMCTRL has an interrupt to handle.
Required properties:
- compatible : should be "brcm,bcm2835-armctrl-ic" or
"brcm,bcm2836-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
1/2" register.
The 2nd cell contains the interrupt number within the bank. Valid values
are 0..7 for bank 0, and 0..31 for bank 1.
Additional required properties for brcm,bcm2836-armctrl-ic:
- interrupts : Specifies the interrupt on the parent for this interrupt
controller to handle.
The interrupt sources are as follows:
Bank 0:
0: ARM_TIMER
1: ARM_MAILBOX
2: ARM_DOORBELL_0
3: ARM_DOORBELL_1
4: VPU0_HALTED
5: VPU1_HALTED
6: ILLEGAL_TYPE0
7: ILLEGAL_TYPE1
Bank 1:
0: TIMER0
1: TIMER1
2: TIMER2
3: TIMER3
4: CODEC0
5: CODEC1
6: CODEC2
7: VC_JPEG
8: ISP
9: VC_USB
10: VC_3D
11: TRANSPOSER
12: MULTICORESYNC0
13: MULTICORESYNC1
14: MULTICORESYNC2
15: MULTICORESYNC3
16: DMA0
17: DMA1
18: VC_DMA2
19: VC_DMA3
20: DMA4
21: DMA5
22: DMA6
23: DMA7
24: DMA8
25: DMA9
26: DMA10
27: DMA11-14 - shared interrupt for DMA 11 to 14
28: DMAALL - triggers on all dma interrupts (including channel 15)
29: AUX
30: ARM
31: VPUDMA
Bank 2:
0: HOSTPORT
1: VIDEOSCALER
2: CCP2TX
3: SDC
4: DSI0
5: AVE
6: CAM0
7: CAM1
8: HDMI0
9: HDMI1
10: PIXELVALVE1
11: I2CSPISLV
12: DSI1
13: PWA0
14: PWA1
15: CPR
16: SMI
17: GPIO0
18: GPIO1
19: GPIO2
20: GPIO3
21: VC_I2C
22: VC_SPI
23: VC_I2SPCM
24: VC_SDIO
25: VC_UART
26: SLIMBUS
27: VEC
28: CPG
29: RNG
30: VC_ARASANSDIO
31: AVSPMON
Example:
/* BCM2835, first level */
intc: interrupt-controller {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* BCM2836, second level */
intc: interrupt-controller {
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
};

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%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM2835 ARMCTRL Interrupt Controller
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
description: >
The BCM2835 contains a custom top-level interrupt controller, which supports
72 interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally as
"armctrl" in the SoC documentation, hence naming of this binding.
The BCM2836 contains the same interrupt controller with the same interrupts,
but the per-CPU interrupt controller is the root, and an interrupt there
indicates that the ARMCTRL has an interrupt to handle.
The interrupt sources are as follows:
Bank 0:
0: ARM_TIMER
1: ARM_MAILBOX
2: ARM_DOORBELL_0
3: ARM_DOORBELL_1
4: VPU0_HALTED
5: VPU1_HALTED
6: ILLEGAL_TYPE0
7: ILLEGAL_TYPE1
Bank 1:
0: TIMER0
1: TIMER1
2: TIMER2
3: TIMER3
4: CODEC0
5: CODEC1
6: CODEC2
7: VC_JPEG
8: ISP
9: VC_USB
10: VC_3D
11: TRANSPOSER
12: MULTICORESYNC0
13: MULTICORESYNC1
14: MULTICORESYNC2
15: MULTICORESYNC3
16: DMA0
17: DMA1
18: VC_DMA2
19: VC_DMA3
20: DMA4
21: DMA5
22: DMA6
23: DMA7
24: DMA8
25: DMA9
26: DMA10
27: DMA11-14 - shared interrupt for DMA 11 to 14
28: DMAALL - triggers on all dma interrupts (including channel 15)
29: AUX
30: ARM
31: VPUDMA
Bank 2:
0: HOSTPORT
1: VIDEOSCALER
2: CCP2TX
3: SDC
4: DSI0
5: AVE
6: CAM0
7: CAM1
8: HDMI0
9: HDMI1
10: PIXELVALVE1
11: I2CSPISLV
12: DSI1
13: PWA0
14: PWA1
15: CPR
16: SMI
17: GPIO0
18: GPIO1
19: GPIO2
20: GPIO3
21: VC_I2C
22: VC_SPI
23: VC_I2SPCM
24: VC_SDIO
25: VC_UART
26: SLIMBUS
27: VEC
28: CPG
29: RNG
30: VC_ARASANSDIO
31: AVSPMON
properties:
compatible:
enum:
- brcm,bcm2835-armctrl-ic
- brcm,bcm2836-armctrl-ic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
description: >
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
1/2" register.
The 2nd cell contains the interrupt number within the bank. Valid values
are 0..7 for bank 0, and 0..31 for bank 1.
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
allOf:
- if:
properties:
compatible:
contains:
const: brcm,bcm2836-armctrl-ic
then:
required:
- interrupts
else:
properties:
interrupts: false
additionalProperties: false
examples:
- |
interrupt-controller@7e00b200 {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
- |
interrupt-controller@7e00b200 {
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <8>;
};

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Broadcom BCM6345-style Level 1 interrupt controller
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU.
Key elements of the hardware design include:
- 32, 64 or 128 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Contains one or more enable/status word pairs per CPU
- No atomic set/clear operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-4 status words to determine which IRQs are pending
Required properties:
- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
- reg: specifies the base physical address and size of the registers;
the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
The driver operates in native CPU endian by default, there is no support for
specifying an alternative endianness.
Example:
periph_intc: interrupt-controller@10000000 {
compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6345-style Level 1 interrupt controller
maintainers:
- Simon Arlott <simon@octiron.net>
description: >
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU.
Key elements of the hardware design include:
- 32, 64 or 128 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Contains one or more enable/status word pairs per CPU
- No atomic set/clear operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-4 status words to determine which IRQs are pending
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
The driver operates in native CPU endian by default, there is no support for
specifying an alternative endianness.
properties:
compatible:
const: brcm,bcm6345-l1-intc
reg:
description: One entry per CPU core
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
description: One entry per CPU core
minItems: 1
maxItems: 2
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@10000000 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <2>, <3>;
};

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* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
Required properties:
- compatible: Should be "cdns,xtensa-mx".
Remaining properties have exact same meaning as in Xtensa PIC
(see cdns,xtensa-pic.txt).
Examples:
pic: pic {
compatible = "cdns,xtensa-mx";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};

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* Xtensa built-in Programmable Interrupt Controller (PIC)
Required properties:
- compatible: Should be "cdns,xtensa-pic".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts.
It may be either 1 or 2.
When it's 1, the first cell is the internal IRQ number.
When it's 2, the first cell is the IRQ number, and the second cell
specifies whether it's internal (0) or external (1).
Periferals are usually connected to a fixed external IRQ, but for different
core variants it may be mapped to different internal IRQ.
IRQ sensitivity and priority are fixed for each core variant and may not be
changed at runtime.
Examples:
pic: pic {
compatible = "cdns,xtensa-pic";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 Max Filippov <jcmvbkbc@gmail.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xtensa Interrupt Controllers
maintainers:
- Max Filippov <jcmvbkbc@gmail.com>
description:
Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and
Xtensa built-in Programmable Interrupt Controller (PIC)
properties:
compatible:
enum:
- cdns,xtensa-mx
- cdns,xtensa-pic
'#interrupt-cells':
enum: [ 1, 2 ]
description:
Number of cells to define the interrupts. When 1, the first cell is the
internal IRQ number; when 2, the second cell specifies internal (0) or
external (1).
interrupt-controller: true
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "cdns,xtensa-pic";
/* one cell: internal irq number,
* two cells: second cell == 0: internal irq number
* second cell == 1: external irq number
*/
#interrupt-cells = <2>;
interrupt-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/chrp,open-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Open PIC Interrupt Controller
maintainers:
- Rob Herring <robh@kernel.org>
description:
This binding specifies what properties must be available in the device tree
representation of an Open PIC compliant interrupt controller. This binding is
based on the binding defined for Open PIC in [1] and is a superset of that
binding.
properties:
compatible:
oneOf:
- items:
- const: fsl,mpic
- const: chrp,open-pic
- const: chrp,open-pic
device_type:
const: open-pci
deprecated: true
reg:
maxItems: 1
interrupt-controller: true
'#address-cells':
const: 0
'#interrupt-cells':
const: 2
pic-no-reset:
description: Indicates the PIC shall not be reset during runtime initialization.
type: boolean
required:
- compatible
- reg
- interrupt-controller
- '#address-cells'
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@40000 {
compatible = "chrp,open-pic";
reg = <0x40000 0x40000>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
pic-no-reset;
};

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Cirrus Logic CLPS711X Interrupt Controller
Required properties:
- compatible: Should be "cirrus,ep7209-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
The interrupt sources are as follows:
ID Name Description
---------------------------
1: BLINT Battery low (FIQ)
3: MCINT Media changed (FIQ)
4: CSINT CODEC sound
5: EINT1 External 1
6: EINT2 External 2
7: EINT3 External 3
8: TC1OI TC1 under flow
9: TC2OI TC2 under flow
10: RTCMI RTC compare match
11: TINT 64Hz tick
12: UTXINT1 UART1 transmit FIFO half empty
13: URXINT1 UART1 receive FIFO half full
14: UMSINT UART1 modem status changed
15: SSEOTI SSI1 end of transfer
16: KBDINT Keyboard
17: SS2RX SSI2 receive FIFO half or greater full
18: SS2TX SSI2 transmit FIFO less than half empty
28: UTXINT2 UART2 transmit FIFO half empty
29: URXINT2 UART2 receive FIFO half full
32: DAIINT DAI interface (FIQ)
Example:
intc: interrupt-controller {
compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CLPS711X Interrupt Controller
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description: >
Cirrus Logic CLPS711X Interrupt Controller
The interrupt sources are as follows:
ID Name Description
---------------------------
1: BLINT Battery low (FIQ)
3: MCINT Media changed (FIQ)
4: CSINT CODEC sound
5: EINT1 External 1
6: EINT2 External 2
7: EINT3 External 3
8: TC1OI TC1 under flow
9: TC2OI TC2 under flow
10: RTCMI RTC compare match
11: TINT 64Hz tick
12: UTXINT1 UART1 transmit FIFO half empty
13: URXINT1 UART1 receive FIFO half full
14: UMSINT UART1 modem status changed
15: SSEOTI SSI1 end of transfer
16: KBDINT Keyboard
17: SS2RX SSI2 receive FIFO half or greater full
18: SS2TX SSI2 transmit FIFO less than half empty
28: UTXINT2 UART2 transmit FIFO half empty
29: URXINT2 UART2 receive FIFO half full
32: DAIINT DAI interface (FIQ)
properties:
compatible:
oneOf:
- items:
- const: cirrus,ep7312-intc
- const: cirrus,ep7209-intc
- items:
- const: cirrus,ep7209-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@80000000 {
compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/cnxt,cx92755-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Conexant Digicolor Interrupt Controller
maintainers:
- Baruch Siach <baruch@tkos.co.il>
description: Conexant Digicolor Interrupt Controller
properties:
compatible:
const: cnxt,cx92755-ic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
syscon:
description: A phandle to the syscon node describing UC registers
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- syscon
additionalProperties: false
examples:
- |
interrupt-controller@f0000040 {
compatible = "cnxt,cx92755-ic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf0000040 0x40>;
syscon = <&uc_regs>;
};

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==============================
C-SKY APB Interrupt Controller
==============================
C-SKY APB Interrupt Controller is a simple soc interrupt controller
on the apb bus and we only use it as root irq controller.
- csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
- csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
- csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
=============================
intc node bindings definition
=============================
Description: Describes APB interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,apb-intc"
"csky,dual-apb-intc"
"csky,gx6605s-intc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: must be <1>
- reg
Usage: required
Value type: <u32 u32>
Definition: <phyaddr size> in soc from cpu view
- interrupt-controller:
Usage: required
- csky,support-pulse-signal:
Usage: select
Description: to support pulse signal flag
Examples:
---------
intc: interrupt-controller@500000 {
compatible = "csky,apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,dual-apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,gx6605s-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/csky,apb-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: C-SKY APB Interrupt Controller
maintainers:
- Guo Ren <guoren@kernel.org>
description: >
C-SKY APB Interrupt Controller is a simple soc interrupt controller on the apb
bus and we only use it as root irq controller.
- csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
- csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
- csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
properties:
compatible:
enum:
- csky,apb-intc
- csky,dual-apb-intc
- csky,gx6605s-intc
reg:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller: true
csky,support-pulse-signal:
type: boolean
description: Support for pulse signal flag.
additionalProperties: false
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
examples:
- |
intc: interrupt-controller@500000 {
compatible = "csky,apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};

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===========================================
C-SKY Multi-processors Interrupt Controller
===========================================
C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
SMP soc, and it also could be used in non-SMP system.
Interrupt number definition:
0-15 : software irq, and we use 15 as our IPI_IRQ.
16-31 : private irq, and we use 16 as the co-processor timer.
31-1024: common irq for soc ip.
Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
IRQ_TYPE_LEVEL_HIGH (default)
IRQ_TYPE_LEVEL_LOW
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
=============================
intc node bindings definition
=============================
Description: Describes SMP interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,mpintc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: <2>
- interrupt-controller:
Usage: required
Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>")
---------
#include <dt-bindings/interrupt-controller/irq.h>
intc: interrupt-controller {
compatible = "csky,mpintc";
#interrupt-cells = <2>;
interrupt-controller;
};
device: device-example {
...
interrupts = <34 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: C-SKY Multi-processors Interrupt Controller
maintainers:
- Guo Ren <guoren@kernel.org>
description: >
C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
SMP soc, and it also could be used in non-SMP system.
Interrupt number definition:
0-15 : software irq, and we use 15 as our IPI_IRQ.
16-31 : private irq, and we use 16 as the co-processor timer.
31-1024: common irq for soc ip.
properties:
compatible:
const: csky,mpintc
'#interrupt-cells':
const: 2
interrupt-controller: true
required:
- compatible
- "#interrupt-cells"
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "csky,mpintc";
#interrupt-cells = <2>;
interrupt-controller;
};

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Conexant Digicolor Interrupt Controller
Required properties:
- compatible : should be "cnxt,cx92755-ic"
- reg : Specifies base physical address and size of the interrupt controller
registers (IC) area
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
- syscon: A phandle to the syscon node describing UC registers
Example:
intc: interrupt-controller@f0000040 {
compatible = "cnxt,cx92755-ic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf0000040 0x40>;
syscon = <&uc_regs>;
};

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EZchip NPS Interrupt Controller
Required properties:
- compatible : should be "ezchip,nps400-ic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
intc: interrupt-controller {
compatible = "ezchip,nps400-ic";
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ezchip,nps400-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EZchip NPS Interrupt Controller
maintainers:
- Noam Camus <noamc@ezchip.com>
properties:
compatible:
const: ezchip,nps400-ic
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "ezchip,nps400-ic";
interrupt-controller;
#interrupt-cells = <1>;
};

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* Faraday Technologt FTINTC010 interrupt controller
This interrupt controller is a stock IP block from Faraday Technology found
in the Gemini SoCs and other designs.
Required properties:
- compatible: must be one of
"faraday,ftintc010"
"cortina,gemini-interrupt-controller" (deprecated)
- reg: The register bank for the interrupt controller.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts.
Must be 2 as the controller can specify level or rising edge
IRQs. The bindings follows the standard binding for controllers
with two cells specified in
interrupt-controller/interrupts.txt
Example:
interrupt-controller@48000000 {
compatible = "faraday,ftintc010"
reg = <0x48000000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/interrupt-controller/faraday,ftintc010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTINTC010 interrupt controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
This interrupt controller is a stock IP block from Faraday Technology found
in the Gemini SoCs and other designs.
properties:
compatible:
oneOf:
- items:
- const: moxa,moxart-ic
- const: faraday,ftintc010
- enum:
- faraday,ftintc010
- cortina,gemini-interrupt-controller
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
resets:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@48000000 {
compatible = "faraday,ftintc010";
reg = <0x48000000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,tzic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale tzic Interrupt controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,imx51-tzic
- fsl,imx53-tzic
- const: fsl,tzic
- items:
- const: fsl,imx50-tzic
- const: fsl,imx53-tzic
- const: fsl,tzic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
tz-interrupt-controller@fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";
reg = <0x0fffc000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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Android Goldfish PIC
Android Goldfish programmable interrupt device used by Android
emulator.
Required properties:
- compatible : should contain "google,goldfish-pic"
- reg : <registers mapping>
- interrupts : <interrupt mapping>
Example for mips when used in cascade mode:
cpuintc {
#interrupt-cells = <0x1>;
#address-cells = <0>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
interrupt-controller@1f000000 {
compatible = "google,goldfish-pic";
reg = <0x1f000000 0x1000>;
interrupt-controller;
#interrupt-cells = <0x1>;
interrupt-parent = <&cpuintc>;
interrupts = <0x2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/google,goldfish-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Android Goldfish PIC
maintainers:
- Miodrag Dinic <miodrag.dinic@mips.com>
description:
Android Goldfish programmable interrupt device used by Android emulator.
properties:
compatible:
const: google,goldfish-pic
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
examples:
- |
interrupt-controller@1f000000 {
compatible = "google,goldfish-pic";
reg = <0x1f000000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <2>;
};
additionalProperties: false

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* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
This binding specifies what properties must be available in the device tree
representation of a PDC IRQ controller. This has a number of input interrupt
lines which can wake the system, and are passed on through output interrupt
lines.
Required properties:
- compatible: Specifies the compatibility list for the interrupt controller.
The type shall be <string> and the value shall include "img,pdc-intc".
- reg: Specifies the base PDC physical address(s) and size(s) of the
addressable register space. The type shall be <prop-encoded-array>.
- interrupt-controller: The presence of this property identifies the node
as an interrupt controller. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- num-perips: Number of waking peripherals.
- num-syswakes: Number of SysWake inputs.
- interrupts: List of interrupt specifiers. The first specifier shall be the
shared SysWake interrupt, and remaining specifies shall be PDC peripheral
interrupts in order.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
0-7: Peripheral interrupts
8-15: SysWake interrupts
- <2nd-cell>: The level-sense information, encoded using the Linux interrupt
flags as follows (only 4 valid for peripheral interrupts):
0 = none (decided by software)
1 = low-to-high edge triggered
2 = high-to-low edge triggered
3 = both edge triggered
4 = active-high level-sensitive (required for perip irqs)
8 = active-low level-sensitive
* Examples
Example 1:
/*
* TZ1090 PDC block
*/
pdc: pdc@02006000 {
// This is an interrupt controller node.
interrupt-controller;
// Three cells to encode interrupt sources.
#interrupt-cells = <2>;
// Offset address of 0x02006000 and size of 0x1000.
reg = <0x02006000 0x1000>;
// Compatible with Meta hardware trigger block.
compatible = "img,pdc-intc";
// Three peripherals are connected.
num-perips = <3>;
// Four SysWakes are connected.
num-syswakes = <4>;
interrupts = <18 4 /* level */>, /* Syswakes */
<30 4 /* level */>, /* Peripheral 0 (RTC) */
<29 4 /* level */>, /* Peripheral 1 (IR) */
<31 4 /* level */>; /* Peripheral 2 (WDT) */
};
Example 2:
/*
* An SoC peripheral that is wired through the PDC.
*/
rtc0 {
// The interrupt controller that this device is wired to.
interrupt-parent = <&pdc>;
// Interrupt source Peripheral 0
interrupts = <0 /* Peripheral 0 (RTC) */
4> /* IRQ_TYPE_LEVEL_HIGH */
};
Example 3:
/*
* An interrupt generating device that is wired to a SysWake pin.
*/
touchscreen0 {
// The interrupt controller that this device is wired to.
interrupt-parent = <&pdc>;
// Interrupt source SysWake 0 that is active-low level-sensitive
interrupts = <8 /* SysWake0 */
8 /* IRQ_TYPE_LEVEL_LOW */>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ImgTec Powerdown Controller (PDC) Interrupt Controller
maintainers:
- James Hogan <jhogan@kernel.org>
description:
ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input
interrupt lines which can wake the system, and are passed on through output
interrupt lines.
properties:
compatible:
const: img,pdc-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description: >
<1st-cell>: The interrupt-number that identifies the interrupt source.
0-7: Peripheral interrupts
8-15: SysWake interrupts
<2nd-cell>: The level-sense information, encoded using the Linux interrupt
flags as follows (only 4 valid for peripheral interrupts):
0 = none (decided by software)
1 = low-to-high edge triggered
2 = high-to-low edge triggered
3 = both edge triggered
4 = active-high level-sensitive (required for perip irqs)
8 = active-low level-sensitive
const: 2
num-perips:
description: Number of waking peripherals
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 8
num-syswakes:
description: Number of SysWake inputs
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 8
interrupts:
description:
First entry is syswake IRQ. Subsequent entries are 1 per peripheral.
minItems: 2
maxItems: 9
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- num-perips
- num-syswakes
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@2006000 {
compatible = "img,pdc-intc";
reg = <0x02006000 0x1000>;
interrupts = <18 4>, <30 4>, <29 4>, <31 4>;
interrupt-controller;
#interrupt-cells = <2>;
num-perips = <3>;
num-syswakes = <4>;
};

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J-Core Advanced Interrupt Controller
Required properties:
- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
the "aic2" core with 64 interrupts.
- reg: Memory region(s) for configuration. For SMP, there should be one
region per cpu, indexed by the sequential, zero-based hardware cpu
number.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
aic: interrupt-controller@200 {
compatible = "jcore,aic2";
reg = < 0x200 0x30 0x500 0x30 >;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/jcore,aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: J-Core Advanced Interrupt Controller
maintainers:
- Rich Felker <dalias@libc.org>
properties:
compatible:
enum:
- jcore,aic1
- jcore,aic2
reg:
description: Memory region(s) for configuration. For SMP, there should be one
region per CPU, indexed by the sequential, zero-based hardware CPU number.
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
aic: interrupt-controller@200 {
compatible = "jcore,aic2";
reg = <0x200 0x30>, <0x500 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
};

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TI-NSPIRE interrupt controller
Required properties:
- compatible: Compatible property value should be "lsi,zevio-intc".
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
Example:
interrupt-controller {
compatible = "lsi,zevio-intc";
interrupt-controller;
reg = <0xDC000000 0x1000>;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 Daniel Tang <dt.tangr@gmail.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/lsi,zevio-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI-NSPIRE Interrupt Controller
maintainers:
- Daniel Tang <dt.tangr@gmail.com>
description: |
TI-NSPIRE interrupt controller
properties:
compatible:
const: lsi,zevio-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@dc000000 {
compatible = "lsi,zevio-intc";
interrupt-controller;
reg = <0xdc000000 0x1000>;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell GICP Controller
maintainers:
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
description:
GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
interrupts by doing a memory transaction. It is used by the ICU
located in the Marvell CP110 to turn wired interrupts inside the CP
into GIC SPI interrupts.
properties:
compatible:
const: marvell,ap806-gicp
reg:
maxItems: 1
marvell,spi-ranges:
description: Tuples of GIC SPI interrupt ranges available for this GICP
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: SPI interrupt base
- description: Number of interrupts in the range
msi-controller: true
required:
- compatible
- reg
- msi-controller
- marvell,spi-ranges
additionalProperties: false
examples:
- |
msi-controller@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell SEI (System Error Interrupt) Controller
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description: >
Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It
receives interrupts from several sources and aggregates them to a single
interrupt line (an SPI) on the parent interrupt controller.
This interrupt controller can handle up to 64 SEIs, a set comes from the AP
and is wired while a second set comes from the CPs by the mean of MSIs.
properties:
compatible:
const: marvell,ap806-sei
reg:
maxItems: 1
interrupts:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller: true
msi-controller: true
required:
- compatible
- reg
- interrupts
- '#interrupt-cells'
- interrupt-controller
- msi-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};

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Marvell Armada 7K/8K PIC Interrupt controller
---------------------------------------------
This is the Device Tree binding for the PIC, a secondary interrupt
controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
typically connected to the GIC as the primary interrupt controller.
Required properties:
- compatible: should be "marvell,armada-8k-pic"
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: the number of cells to define interrupts on this
controller. Should be 1
- reg: the register area for the PIC interrupt controller
- interrupts: the interrupt to the primary interrupt controller,
typically the GIC
Example:
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,armada-8k-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 7K/8K PIC Interrupt controller
maintainers:
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
description:
The Marvell Armada 7K/8K PIC is a secondary interrupt controller available on
the Marvell Armada 7K/8K ARM64 SoCs, and typically connected to the GIC as the
primary interrupt controller.
properties:
compatible:
const: marvell,armada-8k-pic
reg:
maxItems: 1
"#interrupt-cells":
const: 1
interrupt-controller: true
interrupts:
maxItems: 1
description: Interrupt to the primary interrupt controller (GIC).
required:
- compatible
- reg
- "#interrupt-cells"
- interrupt-controller
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,cp110-icu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
title: Marvell ICU Interrupt Controller
description:
The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for
collecting all wired-interrupt sources in the CP and communicating them to the
GIC in the AP. The unit translates interrupt requests on input wires to MSG
memory mapped transactions to the GIC. These messages access different GIC
memory areas depending on their type (NSR, SR, SEI, REI, etc).
properties:
compatible:
const: marvell,cp110-icu
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
patternProperties:
"^interrupt-controller@":
type: object
description: Interrupt group child nodes
additionalProperties: false
properties:
compatible:
enum:
- marvell,cp110-icu-nsr
- marvell,cp110-icu-sr
- marvell,cp110-icu-sei
- marvell,cp110-icu-rei
reg:
maxItems: 1
'#interrupt-cells':
const: 2
interrupt-controller: true
msi-parent:
maxItems: 1
description: Phandle to the GICP controller
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- msi-parent
required:
- compatible
- reg
additionalProperties: false
examples:
- |
interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};

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Marvell GICP Controller
-----------------------
GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
interrupts by doing a memory transaction. It is used by the ICU
located in the Marvell CP110 to turn wired interrupts inside the CP
into GIC SPI interrupts.
Required properties:
- compatible: Must be "marvell,ap806-gicp"
- reg: Must be the address and size of the GICP SPI registers
- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
for this GICP
- msi-controller: indicates that this is an MSI controller
Example:
gicp_spi: gicp-spi@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};

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Marvell ICU Interrupt Controller
--------------------------------
The Marvell ICU (Interrupt Consolidation Unit) controller is
responsible for collecting all wired-interrupt sources in the CP and
communicating them to the GIC in the AP, the unit translates interrupt
requests on input wires to MSG memory mapped transactions to the GIC.
These messages will access a different GIC memory area depending on
their type (NSR, SR, SEI, REI, etc).
Required properties:
- compatible: Should be "marvell,cp110-icu"
- reg: Should contain ICU registers location and length.
Subnodes: Each group of interrupt is declared as a subnode of the ICU,
with their own compatible.
Required properties for the icu_nsr/icu_sei subnodes:
- compatible: Should be one of:
* "marvell,cp110-icu-nsr"
* "marvell,cp110-icu-sr"
* "marvell,cp110-icu-sei"
* "marvell,cp110-icu-rei"
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
The 1st cell is the index of the interrupt in the ICU unit.
The 2nd cell is the type of the interrupt. See arm,gic.txt for
details.
- interrupt-controller: Identifies the node as an interrupt
controller.
- msi-parent: Should point to the GICP controller, the GIC extension
that allows to trigger interrupts using MSG memory mapped
transactions.
Note: each 'interrupts' property referring to any 'icu_xxx' node shall
have a different number within [0:206].
Example:
icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
CP110_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
node1 {
interrupt-parent = <&icu_nsr>;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
};
node2 {
interrupt-parent = <&icu_sei>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};
/* Would not work with the above nodes */
node3 {
interrupt-parent = <&icu_nsr>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};
The legacy bindings were different in this way:
- #interrupt-cells: The value was 3.
The 1st cell was the group type of the ICU interrupt. Possible
group types were:
ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
ICU_GRP_SEI (0x4) : System error interrupt
ICU_GRP_REI (0x5) : RAM error interrupt
The 2nd cell was the index of the interrupt in the ICU unit.
The 3rd cell was the type of the interrupt. See arm,gic.txt for
details.
Example:
icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
node1 {
interrupt-parent = <&icu>;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
};

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* Marvell ODMI for MSI support
Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
which can be used by on-board peripheral for MSI interrupts.
Required properties:
- compatible : The value here should contain:
"marvell,ap806-odmi-controller", "marvell,odmi-controller".
- interrupt,controller : Identifies the node as an interrupt controller.
- msi-controller : Identifies the node as an MSI controller.
- marvell,odmi-frames : Number of ODMI frames available. Each frame
provides a number of events.
- reg : List of register definitions, one for each
ODMI frame.
- marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding.
Example:
odmi: odmi@300000 {
compatible = "marvell,ap806-odmi-controller",
"marvell,odmi-controller";
interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
<0x304000 0x4000>,
<0x308000 0x4000>,
<0x30C000 0x4000>;
marvell,spi-base = <128>, <136>, <144>, <152>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell ODMI controller
maintainers:
- Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
description:
Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
be used by on-board peripherals for MSI interrupts.
properties:
compatible:
const: marvell,odmi-controller
reg:
description: List of register definitions, one for each ODMI frame.
msi-controller: true
marvell,odmi-frames:
description: Number of ODMI frames available. Each frame provides a number of events.
$ref: /schemas/types.yaml#/definitions/uint32
marvell,spi-base:
description: >
List of GIC base SPI interrupts, one for each ODMI frame. Those SPI
interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details.
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- msi-controller
- marvell,odmi-frames
- marvell,spi-base
additionalProperties: false
examples:
- |
msi-controller@300000 {
compatible = "marvell,odmi-controller";
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>;
marvell,spi-base = <128>, <136>, <144>, <152>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,orion-bridge-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Orion SoC Bridge Interrupt Controller
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
const: marvell,orion-bridge-intc
reg:
minItems: 1
maxItems: 2
interrupt-controller: true
'#interrupt-cells':
const: 1
interrupts:
description: Bridge interrupt of the main interrupt controller
marvell,#interrupts:
description: Number of interrupts provided by bridge interrupt controller.
$ref: /schemas/types.yaml#/definitions/uint32
default: 32
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@20110 {
compatible = "marvell,orion-bridge-intc";
reg = <0x20110 0x8>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <0>;
/* Dove bridge provides 5 interrupts */
marvell,#interrupts = <5>;
};

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Marvell Orion SoC interrupt controllers
* Main interrupt controller
Required properties:
- compatible: shall be "marvell,orion-intc"
- reg: base address(es) of interrupt registers starting with CAUSE register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of first base address,
- 1 maps to bit 1 of first base address,
- 32 maps to bit 0 of second base address, and so on.
Example:
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
/* Dove has 64 first level interrupts */
reg = <0x20200 0x10>, <0x20210 0x10>;
};
* Bridge interrupt controller
Required properties:
- compatible: shall be "marvell,orion-bridge-intc"
- reg: base address of bridge interrupt registers starting with CAUSE register
- interrupts: bridge interrupt of the main interrupt controller
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
Optional properties:
- marvell,#interrupts: number of interrupts provided by bridge interrupt
controller, defaults to 32 if not set
Example:
bridge_intc: interrupt-controller {
compatible = "marvell,orion-bridge-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20110 0x8>;
interrupts = <0>;
/* Dove bridge provides 5 interrupts */
marvell,#interrupts = <5>;
};

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Marvell SEI (System Error Interrupt) Controller
-----------------------------------------------
Marvell SEI (System Error Interrupt) controller is an interrupt
aggregator. It receives interrupts from several sources and aggregates
them to a single interrupt line (an SPI) on the parent interrupt
controller.
This interrupt controller can handle up to 64 SEIs, a set comes from the
AP and is wired while a second set comes from the CPs by the mean of
MSIs.
Required properties:
- compatible: should be one of:
* "marvell,ap806-sei"
- reg: SEI registers location and length.
- interrupts: identifies the parent IRQ that will be triggered.
- #interrupt-cells: number of cells to define an SEI wired interrupt
coming from the AP, should be 1. The cell is the IRQ
number.
- interrupt-controller: identifies the node as an interrupt controller
for AP interrupts.
- msi-controller: identifies the node as an MSI controller for the CPs
interrupts.
Example:
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};

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Microchip PIC32 Interrupt Controller
====================================
The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
It handles all internal and external interrupts. This controller exists outside
of the CPU and is the arbitrator of all interrupts (including interrupts from
the CPU itself) before they are presented to the CPU.
External interrupts have a software configurable edge polarity. Non external
interrupts have a type and polarity that is determined by the source of the
interrupt.
Required properties
-------------------
- compatible: Should be "microchip,pic32mzda-evic"
- reg: Specifies physical base address and size of register range.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
source connected to this controller. The value shall be 2 and interrupt
descriptor shall have the following format:
<hw_irq irq_type>
hw_irq - represents the hardware interrupt number as in the data sheet.
irq_type - is used to describe the type and polarity of an interrupt. For
internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
Optional properties
-------------------
- microchip,external-irqs: u32 array of external interrupts with software
polarity configuration. This array corresponds to the bits in the INTCON
SFR.
Example
-------
evic: interrupt-controller@1f810000 {
compatible = "microchip,pic32mzda-evic";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1f810000 0x1000>;
microchip,external-irqs = <3 8 13 18 23>;
};
Each device/peripheral must request its interrupt line with the associated type
and polarity.
Internal interrupt DTS snippet
------------------------------
device@1f800000 {
...
interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
...
};
External interrupt DTS snippet
------------------------------
device@1f800000 {
...
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
...
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIC32 EVIC Interrupt Controller
maintainers:
- Cristian Birsan <cristian.birsan@microchip.com>
description: >
The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
It handles all internal and external interrupts. This controller exists
outside of the CPU and is the arbitrator of all interrupts (including
interrupts from the CPU itself) before they are presented to the CPU.
External interrupts have a software configurable edge polarity. Non external
interrupts have a type and polarity that is determined by the source of the
interrupt.
properties:
compatible:
items:
- const: microchip,pic32mzda-evic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
microchip,external-irqs:
description:
External interrupts with software polarity configuration corresponding to
the INTCON SFR bits.
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@1f810000 {
compatible = "microchip,pic32mzda-evic";
reg = <0x1f810000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
microchip,external-irqs = <3 8 13 18 23>;
};

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* Open PIC Binding
This binding specifies what properties must be available in the device tree
representation of an Open PIC compliant interrupt controller. This binding is
based on the binding defined for Open PIC in [1] and is a superset of that
binding.
Required properties:
NOTE: Many of these descriptions were paraphrased here from [1] to aid
readability.
- compatible: Specifies the compatibility list for the PIC. The type
shall be <string> and the value shall include "open-pic".
- reg: Specifies the base physical address(s) and size(s) of this
PIC's addressable register space. The type shall be <prop-encoded-array>.
- interrupt-controller: The presence of this property identifies the node
as an Open PIC. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- #address-cells: Specifies the number of cells needed to encode an
address. The type shall be <u32> and the value shall be 0. As such,
'interrupt-map' nodes do not have to specify a parent unit address.
Optional properties:
- pic-no-reset: The presence of this property indicates that the PIC
shall not be reset during runtime initialization. No property value shall
be defined. The presence of this property also mandates that any
initialization related to interrupt sources shall be limited to sources
explicitly referenced in the device tree.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as
follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
- <2nd-cell>: The level-sense information, encoded as follows:
0 = low-to-high edge triggered
1 = active low level-sensitive
2 = active high level-sensitive
3 = high-to-low edge triggered
* Examples
Example 1:
/*
* An Open PIC interrupt controller
*/
mpic: pic@40000 {
// This is an interrupt controller node.
interrupt-controller;
// No address cells so that 'interrupt-map' nodes which reference
// this Open PIC node do not need a parent address specifier.
#address-cells = <0>;
// Two cells to encode interrupt sources.
#interrupt-cells = <2>;
// Offset address of 0x40000 and size of 0x40000.
reg = <0x40000 0x40000>;
// Compatible with Open PIC.
compatible = "open-pic";
// The PIC shall not be reset.
pic-no-reset;
};
Example 2:
/*
* An interrupt generating device that is wired to an Open PIC.
*/
serial0: serial@4500 {
// Interrupt source '42' that is active high level-sensitive.
// Note that there are only two cells as specified in the interrupt
// parent's '#interrupt-cells' property.
interrupts = <42 2>;
// The interrupt controller that this device is wired to.
interrupt-parent = <&mpic>;
};
* References
[1] Devicetree Specification
(https://www.devicetree.org/specifications/)

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros ath79 CPU interrupt controller
maintainers:
- Alban Bedel <albeu@free.fr>
description:
On most SoC the IRQ controller need to flush the DDR FIFO before running the
interrupt handler of some devices. This is configured using the
qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-cpu-intc
- const: qca,ar7100-cpu-intc
- items:
- const: qca,ar7100-cpu-intc
interrupt-controller: true
'#interrupt-cells':
const: 1
qca,ddr-wb-channel-interrupts:
description: List of interrupts needing a write buffer flush
$ref: /schemas/types.yaml#/definitions/uint32-array
qca,ddr-wb-channels:
description: List of write buffer channel phandles for each interrupt
$ref: /schemas/types.yaml#/definitions/phandle-array
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
ddr_ctrl: memory-controller {
#qca,ddr-wb-channel-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
maintainers:
- Alban Bedel <albeu@free.fr>
- Alexander Couzens <lynxis@fe80.eu>
description:
The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary
controller for lower priority interrupts.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-misc-intc
- const: qca,ar7100-misc-intc
- const: qca,ar7240-misc-intc
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
examples:
- |
interrupt-controller@18060010 {
compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
reg = <0x18060010 0x4>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};

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Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
On most SoC the IRQ controller need to flush the DDR FIFO before running
the interrupt handler of some devices. This is configured using the
qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
as fallback
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 1 for intc
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Optional Properties:
- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
buffer flush
- qca,ddr-wb-channels: List of phandles to the write buffer channels for
each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
default to the entry's index.
Example:
interrupt-controller {
compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
...
ddr_ctrl: memory-controller@18000000 {
...
#qca,ddr-wb-channel-cells = <1>;
};

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Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
The MISC interrupt controller is a secondary controller for lower priority
interrupt.
Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
- reg: Base address and size of the controllers memory area
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 1
Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
use ar7240 for all other SoCs.
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
interrupt-controller@18060010 {
compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};
Another example:
interrupt-controller@18060010 {
compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};

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* ARC700 incore Interrupt Controller
The core interrupt controller provides 32 prioritised interrupts (2 levels)
to ARC700 core.
Properties:
- compatible: "snps,arc700-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.
Single Cell "interrupts" property of a device specifies the IRQ number
between 0 to 31
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
Example:
intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/snps,arc700-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARC700 incore Interrupt Controller
maintainers:
- Vineet Gupta <vgupta@kernel.org>
description: >
The core interrupt controller provides 32 prioritized interrupts (2 levels)
to ARC700 core.
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
properties:
compatible:
const: snps,arc700-intc
interrupt-controller: true
'#interrupt-cells':
description: An interrupt number 0-31
const: 1
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
};

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* ARC-HS Interrupt Distribution Unit
This optional 2nd level interrupt controller can be used in SMP configurations
for dynamic IRQ routing, load balancing of common/external IRQs towards core
intc.
Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1> or <2>.
Value of the first cell specifies the "common" IRQ from peripheral to IDU.
Number N of the particular interrupt line of IDU corresponds to the line N+24
of the core interrupt controller.
The (optional) second cell specifies any of the following flags:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = NOT SUPPORTED (high-to-low edge triggered)
4 = active high level-sensitive <<< DEFAULT
8 = NOT SUPPORTED (active low level-sensitive)
When no second cell is specified, the interrupt is assumed to be level
sensitive.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.
Example:
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <1>;
};
some_device: serial@c0fc1000 {
interrupt-parent = <&idu_intc>;
interrupts = <0>; /* upstream idu IRQ #24 */
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARC-HS Interrupt Distribution Unit
maintainers:
- Vineet Gupta <vgupta@kernel.org>
description: >
ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
controller which can be used in SMP configurations for dynamic IRQ routing,
load balancing of common/external IRQs towards core intc.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.
properties:
compatible:
const: snps,archs-idu-intc
interrupt-controller: true
'#interrupt-cells':
description: |
Number of interrupt specifier cells:
- 1: only a common IRQ is specified.
- 2: a second cell encodes trigger type and level flags:
1 = low-to-high edge triggered
4 = active high level-sensitive (default)
enum: [1, 2]
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};

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* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
Properties:
- compatible: "snps,archs-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.
Single Cell "interrupts" property of a device specifies the IRQ number
between 16 to 256
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
Example:
intc: interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <16 17 18 19 20 21 22 23 24 25>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARC-HS incore Interrupt Controller
maintainers:
- Vineet Gupta <vgupta@kernel.org>
description:
ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA.
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
properties:
compatible:
const: snps,archs-intc
interrupt-controller: true
'#interrupt-cells':
const: 1
interrupts:
description: List of IRQ numbers between 16 and 256
items:
items:
- minimum: 16
maximum: 256
required:
- compatible
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>;
};

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Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
controller in some SoCs, e.g. Hisilicon SD5203.
Required properties:
- compatible: shall be "snps,dw-apb-ictl"
- reg: physical base address of the controller and length of memory mapped
region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
Additional required property when it's used as secondary interrupt controller:
- interrupts: interrupt reference to primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of low interrupts,
- 1 maps to bit 1 of low interrupts,
- 32 maps to bit 0 of high interrupts,
- 33 maps to bit 1 of high interrupts,
- (optional) fast interrupts start at 64.
Example:
/* dw_apb_ictl is used as secondary interrupt controller */
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
/* dw_apb_ictl is used as primary interrupt controller */
vic: interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare APB interrupt controller
maintainers:
- Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- Zhen Lei <thunder.leizhen@huawei.com>
description:
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs
with APB bus, e.g. Marvell Armada 1500. It can also be used as primary
interrupt controller in some SoCs, e.g. Hisilicon SD5203.
properties:
compatible:
const: snps,dw-apb-ictl
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 1
interrupts:
maxItems: 1
description: >
Interrupt input connected to the primary interrupt controller when used
as a secondary controller. The interrupt specifier maps to bits in the
low and high interrupt registers (0⇒bit 0 low, 1⇒bit 1 low, 32⇒bit 0 high,
33⇒bit 1 high, fast interrupts start at 64).
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
- |
interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPEAr3xx Shared IRQ controller
maintainers:
- Viresh Kumar <vireshk@kernel.org>
- Shiraz Hashim <shiraz.linux.kernel@gmail.com>
description: |
SPEAr3xx architecture includes shared/multiplexed irqs for certain set of
devices. The multiplexor provides a single interrupt to parent interrupt
controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not exceeding
4. The number of devices in a group can differ, further they may share same
set of status/mask registers spanning across different bit masks. Also in some
cases the group may not have enable or other registers. This makes software
little complex.
A single node in the device tree is used to describe the shared interrupt
multiplexer (one node for all groups). A group in the interrupt controller
shares config/control registers with other groups. For example, a 32-bit
interrupt enable/disable config register can accommodate up to 4 interrupt
groups.
properties:
compatible:
enum:
- st,spear300-shirq
- st,spear310-shirq
- st,spear320-shirq
reg:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller: true
interrupts:
description: Interrupt specifier array for SHIRQ groups
minItems: 1
maxItems: 4
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <28 29 30 1>;
#interrupt-cells = <1>;
interrupt-controller;
};

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* SPEAr Shared IRQ layer (shirq)
SPEAr3xx architecture includes shared/multiplexed irqs for certain set
of devices. The multiplexor provides a single interrupt to parent
interrupt controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not
exceeding 4. The number of devices in a group can differ, further they
may share same set of status/mask registers spanning across different
bit masks. Also in some cases the group may not have enable or other
registers. This makes software little complex.
A single node in the device tree is used to describe the shared
interrupt multiplexor (one node for all groups). A group in the
interrupt controller shares config/control registers with other groups.
For example, a 32-bit interrupt enable/disable config register can
accommodate up to 4 interrupt groups.
Required properties:
- compatible: should be, either of
- "st,spear300-shirq"
- "st,spear310-shirq"
- "st,spear320-shirq"
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <1> which basically contains the offset
(starting from 0) of interrupts for all the groups.
- reg: Base address and size of shirq registers.
- interrupts: The list of interrupts generated by the groups which are
then connected to a parent interrupt controller. Each group is
associated with one of the interrupts, hence number of interrupts (to
parent) is equal to number of groups. The format of the interrupt
specifier depends in the interrupt parent controller.
Example:
The following is an example from the SPEAr320 SoC dtsi file.
shirq: interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <28 29 30 1>;
#interrupt-cells = <1>;
interrupt-controller;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/technologic,ts4800-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TS-4800 FPGA Interrupt Controller
maintainers:
- Damien Riegel <damien.riegel@savoirfairelinux.com>
description:
TS-4800 FPGA has an internal interrupt controller. When one of the interrupts
is triggered, the SoC is notified, usually using a GPIO as parent interrupt
source.
properties:
compatible:
const: technologic,ts4800-irqc
reg:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller: true
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@1000 {
compatible = "technologic,ts4800-irqc";
reg = <0x1000 0x80>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <10>;
};

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TS-4800 FPGA interrupt controller
TS-4800 FPGA has an internal interrupt controller. When one of the
interrupts is triggered, the SoC is notified, usually using a GPIO as
parent interrupt source.
Required properties:
- compatible: should be "technologic,ts4800-irqc"
- interrupt-controller: identifies the node as an interrupt controller
- reg: physical base address of the controller and length of memory mapped
region
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupts: specifies the interrupt line in the interrupt-parent controller

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* TI Common Platform Interrupt Controller
Common Platform Interrupt Controller (cp_intc) is used on
OMAP-L1x SoCs and can support several configurable number
of interrupts.
Main node required properties:
- compatible : should be:
"ti,cp-intc"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 1.
The cell contains the interrupt number in the range [0-128].
- ti,intc-size: Number of interrupts handled by the interrupt controller.
- reg: physical base address and size of the intc registers map.
Example:
intc: interrupt-controller@1 {
compatible = "ti,cp-intc";
interrupt-controller;
#interrupt-cells = <1>;
ti,intc-size = <101>;
reg = <0xfffee000 0x2000>;
};

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