From 5d2b897bc6f5e8adfe43c0a8cf4c483f2154bf2c Mon Sep 17 00:00:00 2001 From: Chun-Jie Chen Date: Tue, 27 Jul 2021 10:32:04 +0800 Subject: [PATCH 1/9] arm64: dts: mediatek: Add mt8192 clock controllers Add clock controller nodes for SoC mt8192 Signed-off-by: Weiyi Lu Signed-off-by: Chun-Jie Chen Reviewed-by: Ikjoon Jang Link: https://lore.kernel.org/r/20210727023205.20319-2-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9757138a8bbd..c7c7d4e017ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include #include #include @@ -257,6 +258,24 @@ ppi_cluster1: interrupt-partition-1 { }; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt8192-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8192-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt8192-pinctrl"; reg = <0 0x10005000 0 0x1000>, @@ -282,6 +301,12 @@ pio: pinctrl@10005000 { #interrupt-cells = <2>; }; + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8192-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8192-timer", "mediatek,mt6765-timer"; @@ -291,6 +316,12 @@ systimer: timer@10017000 { clock-names = "clk13m"; }; + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8192-scp_adsp"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8192-uart", "mediatek,mt6577-uart"; @@ -311,6 +342,12 @@ uart1: serial@11003000 { status = "disabled"; }; + imp_iic_wrap_c: clock-controller@11007000 { + compatible = "mediatek,mt8192-imp_iic_wrap_c"; + reg = <0 0x11007000 0 0x1000>; + #clock-cells = <1>; + }; + spi0: spi@1100a000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -436,6 +473,12 @@ nor_flash: spi@11234000 { status = "disable"; }; + audsys: clock-controller@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + i2c3: i2c3@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, @@ -449,6 +492,12 @@ i2c3: i2c3@11cb0000 { status = "disabled"; }; + imp_iic_wrap_e: clock-controller@11cb1000 { + compatible = "mediatek,mt8192-imp_iic_wrap_e"; + reg = <0 0x11cb1000 0 0x1000>; + #clock-cells = <1>; + }; + i2c7: i2c7@11d00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d00000 0 0x1000>, @@ -488,6 +537,12 @@ i2c9: i2c9@11d02000 { status = "disabled"; }; + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8192-imp_iic_wrap_s"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + i2c1: i2c1@11d20000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d20000 0 0x1000>, @@ -527,6 +582,12 @@ i2c4: i2c4@11d22000 { status = "disabled"; }; + imp_iic_wrap_ws: clock-controller@11d23000 { + compatible = "mediatek,mt8192-imp_iic_wrap_ws"; + reg = <0 0x11d23000 0 0x1000>; + #clock-cells = <1>; + }; + i2c5: i2c5@11e00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11e00000 0 0x1000>, @@ -540,6 +601,12 @@ i2c5: i2c5@11e00000 { status = "disabled"; }; + imp_iic_wrap_w: clock-controller@11e01000 { + compatible = "mediatek,mt8192-imp_iic_wrap_w"; + reg = <0 0x11e01000 0 0x1000>; + #clock-cells = <1>; + }; + i2c0: i2c0@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, @@ -565,5 +632,101 @@ i2c6: i2c6@11f01000 { #size-cells = <0>; status = "disabled"; }; + + imp_iic_wrap_n: clock-controller@11f02000 { + compatible = "mediatek,mt8192-imp_iic_wrap_n"; + reg = <0 0x11f02000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc_top: clock-controller@11f10000 { + compatible = "mediatek,mt8192-msdc_top"; + reg = <0 0x11f10000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc: clock-controller@11f60000 { + compatible = "mediatek,mt8192-msdc"; + reg = <0 0x11f60000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8192-mfgcfg"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8192-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt8192-imgsys"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: clock-controller@15820000 { + compatible = "mediatek,mt8192-imgsys2"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: clock-controller@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1602f000 { + compatible = "mediatek,mt8192-vdecsys"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8192-vencsys"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt8192-camsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible = "mediatek,mt8192-camsys_rawa"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible = "mediatek,mt8192-camsys_rawb"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawc: clock-controller@1a08f000 { + compatible = "mediatek,mt8192-camsys_rawc"; + reg = <0 0x1a08f000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt8192-ipesys"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: clock-controller@1f000000 { + compatible = "mediatek,mt8192-mdpsys"; + reg = <0 0x1f000000 0 0x1000>; + #clock-cells = <1>; + }; }; }; From 13dd23cfc6e2592220f2721e0ba6e4e105b2a0e2 Mon Sep 17 00:00:00 2001 From: Kansho Nishida Date: Tue, 6 Jul 2021 19:01:35 +0900 Subject: [PATCH 2/9] arm64: dts: mt8183: add audio node Add afe (audio front end) device node to the MT8183 dtsi. Signed-off-by: Kansho Nishida Link: https://lore.kernel.org/r/20210706190111.v3.1.I88a52644e47e88b15f5db9841cb084dc53c5875c@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 94 +++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 409cf827970c..9ea4c5001b1e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1115,10 +1115,102 @@ usb_host: usb@11200000 { }; }; - audiosys: syscon@11220000 { + audiosys: audio-controller@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; #clock-cells = <1>; + afe: mt8183-afe-pcm { + compatible = "mediatek,mt8183-audio"; + interrupts = ; + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + power-domains = + <&spm MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_I2S1>, + <&audiosys CLK_AUDIO_I2S2>, + <&audiosys CLK_AUDIO_I2S3>, + <&audiosys CLK_AUDIO_I2S4>, + <&audiosys CLK_AUDIO_TDM>, + <&audiosys CLK_AUDIO_TML>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&topckgen CLK_TOP_MUX_AUD_1>, + <&topckgen CLK_TOP_APLL1_CK>, + <&topckgen CLK_TOP_MUX_AUD_2>, + <&topckgen CLK_TOP_APLL2_CK>, + <&topckgen CLK_TOP_MUX_AUD_ENG1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_MUX_AUD_ENG2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_MUX_APLL_I2S0>, + <&topckgen CLK_TOP_MUX_APLL_I2S1>, + <&topckgen CLK_TOP_MUX_APLL_I2S2>, + <&topckgen CLK_TOP_MUX_APLL_I2S3>, + <&topckgen CLK_TOP_MUX_APLL_I2S4>, + <&topckgen CLK_TOP_MUX_APLL_I2S5>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adc_adda6_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_i2s1_bclk_sw", + "aud_i2s2_bclk_sw", + "aud_i2s3_bclk_sw", + "aud_i2s4_bclk_sw", + "aud_tdm_clk", + "aud_tml_clk", + "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_syspll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + /*"top_apll12_div5",*/ + "top_clk26m_clk"; + }; }; mmc0: mmc@11230000 { From d2bbd5d96b03f0367da71c6f990851126f24b5b0 Mon Sep 17 00:00:00 2001 From: Kansho Nishida Date: Tue, 6 Jul 2021 19:01:36 +0900 Subject: [PATCH 3/9] arm64: dts: mt8183: add kukui platform audio node Set pin control for the SoC sound node. The compatibles are set by each model dts. The codecs that each models use are: burnet ts3a227_max98357 damu da7219_max98357 fennel da7219_rt1015p fennel14 da7219_rt1015p juniper ts3a227_max98357 kakadu da7219_rt1015p kappa ts3a227_max98357 kenzo ts3a227_max98357 kodama ts3a227_max98357 krane ts3a227_max98357 willow-sku0 da7219_max98357 willow-sku1 ts3a227_max98357 Signed-off-by: Kansho Nishida Link: https://lore.kernel.org/r/20210706190111.v3.2.I6e9ce0f2a489f9a52299656cd966b38ae75e7552@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6358.dtsi | 1 + .../mt8183-kukui-audio-da7219-max98357a.dtsi | 13 ++++ .../mt8183-kukui-audio-da7219-rt1015p.dtsi | 13 ++++ .../mediatek/mt8183-kukui-audio-da7219.dtsi | 54 +++++++++++++++ .../mt8183-kukui-audio-max98357a.dtsi | 13 ++++ .../mediatek/mt8183-kukui-audio-rt1015p.dtsi | 13 ++++ ...mt8183-kukui-audio-ts3a227e-max98357a.dtsi | 13 ++++ .../mt8183-kukui-audio-ts3a227e-rt1015p.dtsi | 13 ++++ .../mediatek/mt8183-kukui-audio-ts3a227e.dtsi | 32 +++++++++ .../mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + .../mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + .../mediatek/mt8183-kukui-jacuzzi-fennel.dtsi | 1 + .../mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + .../mediatek/mt8183-kukui-jacuzzi-kappa.dts | 1 + .../mediatek/mt8183-kukui-jacuzzi-kenzo.dts | 1 + .../mt8183-kukui-jacuzzi-willow-sku0.dts | 1 + .../mt8183-kukui-jacuzzi-willow-sku1.dts | 1 + .../boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + .../dts/mediatek/mt8183-kukui-kodama.dtsi | 1 + .../boot/dts/mediatek/mt8183-kukui-krane.dtsi | 5 ++ .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 67 +++++++++++++++++-- 21 files changed, 243 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi index fa159b20379e..95145076b7e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -13,6 +13,7 @@ pmic: mt6358 { mt6358codec: mt6358codec { compatible = "mediatek,mt6358-sound"; + mediatek,dmic-mode = <0>; /* two-wires */ }; mt6358regulator: mt6358regulator { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi new file mode 100644 index 000000000000..e4aeea4599f5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) da7219-max98357a sound card. + * + * Copyright 2019 Google LLC. + */ + +#include "mt8183-kukui-audio-da7219.dtsi" +#include "mt8183-kukui-audio-max98357a.dtsi" + +&sound { + compatible = "mediatek,mt8183_da7219_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi new file mode 100644 index 000000000000..16ce5a3612ee --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) da7219-rt1015p sound card. + * + * Copyright 2020 Google LLC. + */ + +#include "mt8183-kukui-audio-da7219.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +&sound { + compatible = "mediatek,mt8183_da7219_rt1015p"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi new file mode 100644 index 000000000000..2c69e7658dba --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for da7219. + * + * Copyright 2020 Google LLC. + */ + +&i2c5 { + da7219: da7219@1a { + pinctrl-names = "default"; + pinctrl-0 = <&da7219_pins>; + compatible = "dlg,da7219"; + reg = <0x1a>; + interrupt-parent = <&pio>; + interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>; + + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + VDD-supply = <&pp1800_alw>; + VDDMIC-supply = <&pp3300_alw>; + VDDIO-supply = <&pp1800_alw>; + + status = "okay"; + + da7219_aad { + dlg,adc-1bit-rpt = <1>; + dlg,btn-avg = <4>; + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3E>; + }; + }; +}; + +&pio { + da7219_pins: da7219_pins { + pins1 { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; +}; + +&sound { + mediatek,headset-codec = <&da7219>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi new file mode 100644 index 000000000000..2b60967c0c1c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for max98357a. + * + * Copyright 2020 Google LLC. + */ + +/ { + max98357a: max98357a { + compatible = "maxim,max98357a"; + sdmode-gpios = <&pio 175 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi new file mode 100644 index 000000000000..658a764fe9ee --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for rt1015p. + * + * Copyright 2020 Google LLC. + */ + +/ { + rt1015p: rt1015p { + compatible = "realtek,rt1015p"; + sdb-gpios = <&pio 175 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi new file mode 100644 index 000000000000..260a5f561495 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) ts3a227e-max98357a sound card. + * + * Copyright 2020 Google LLC. + */ + +#include "mt8183-kukui-audio-max98357a.dtsi" +#include "mt8183-kukui-audio-ts3a227e.dtsi" + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi new file mode 100644 index 000000000000..2f7d1fa1c90f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card. + * + * Copyright 2021 Google LLC. + */ + +#include "mt8183-kukui-audio-ts3a227e.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi new file mode 100644 index 000000000000..0799c48ade19 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for ts3a227e. + * + * Copyright 2019 Google LLC. + */ + +&i2c5 { + ts3a227e: ts3a227e@3b { + pinctrl-names = "default"; + pinctrl-0 = <&ts3a227e_pins>; + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&pio>; + interrupts = <157 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; +}; + +&pio { + ts3a227e_pins: ts3a227e_pins { + pins1 { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; +}; + +&sound { + mediatek,headset-codec = <&ts3a227e>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts index a8d6f32ade8d..1a2ec0787d3c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { model = "Google burnet board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts index 42ba9c00866c..0eca3ff8672a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-da7219-max98357a.dtsi" / { model = "Google damu board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi index bbe6c338f465..577519a775c0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" &mt6358codec { mediatek,dmic-mode = <1>; /* one-wire */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts index 36d2c3b3cadf..bc2c57f0a827 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-juniper.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { model = "Google juniper sku16 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts index b3f46c16e5d7..e5bd9191e426 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { model = "Google kappa board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts index 6f1aa692753a..8fa89db03e63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-juniper.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { model = "Google kenzo sku17 board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts index 281265f082db..89208b843b27 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-willow.dtsi" +#include "mt8183-kukui-audio-da7219-max98357a.dtsi" / { model = "Google willow board sku0"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts index 22e56bdc1ee3..c7b20441d053 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi-willow.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { model = "Google willow board sku1"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts index 20eb0dc68f09..89a139a0ee44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui-kakadu.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" / { model = "MediaTek kakadu board"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index 3aa79403c0c2..06f8c80bf553 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8183-kukui.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" / { ppvarn_lcd: ppvarn-lcd { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index 30c183c96a54..a7b0cb3ff7b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -4,6 +4,7 @@ */ #include "mt8183-kukui.dtsi" +#include "mt8183-kukui-audio-max98357a.dtsi" / { ppvarn_lcd: ppvarn-lcd { @@ -345,3 +346,7 @@ rst_pin { &qca_wifi { qcom,ath10k-calibration-variant = "LE_Krane"; }; + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 8e9cf36a9a41..b42d81d26d72 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -115,12 +115,18 @@ scp_mem_reserved: scp_mem_region { }; }; - max98357a: codec0 { - compatible = "maxim,max98357a"; - sdmode-gpios = <&pio 175 0>; + sound: mt8183-sound { + mediatek,platform = <&afe>; + pinctrl-names = "default", + "aud_tdm_out_on", + "aud_tdm_out_off"; + pinctrl-0 = <&aud_pins_default>; + pinctrl-1 = <&aud_pins_tdm_out_on>; + pinctrl-2 = <&aud_pins_tdm_out_off>; + status = "okay"; }; - btsco: codec1 { + btsco: bt-sco { compatible = "linux,bt-sco"; }; @@ -215,6 +221,11 @@ tboard_thermistor2: thermal-sensor2 { }; }; +&afe { + i2s3-share = "I2S2"; + i2s0-share = "I2S5"; +}; + &auxadc { status = "okay"; }; @@ -402,6 +413,54 @@ &mt6358_vsim2_reg { }; &pio { + aud_pins_default: audiopins { + pins_bus { + pinmux = , + , + , + , + , /*i2s to da7219/max98357*/ + , + , + , + , /*i2s to wifi/bt*/ + , + , + , + , + , + , + , + ; /*mtkaif3.0*/ + }; + }; + + aud_pins_tdm_out_on: audiotdmouton { + pins_bus { + pinmux = , + , + , + , + , + ; /*8ch-i2s to it6505*/ + drive-strength = ; + }; + }; + + aud_pins_tdm_out_off: audiotdmoutoff { + pins_bus { + pinmux = , + , + , + , + , + ; + input-enable; + bias-pull-down; + drive-strength = ; + }; + }; + bt_pins: bt-pins { pins_bt_en { pinmux = ; From c99c4733d2ea39a4f37fa9c21e326e6b7ee8c7ec Mon Sep 17 00:00:00 2001 From: Chuanjia Liu Date: Mon, 23 Aug 2021 11:27:59 +0800 Subject: [PATCH 4/9] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 There are two independent PCIe controllers in MT2712 and MT7622 platform. Each of them should contain an independent MSI domain. In old dts architecture, MSI domain will be inherited from the root bridge, and all of the devices will share the same MSI domain. Hence that, the PCIe devices will not work properly if the irq number which required is more than 32. Split the PCIe node for MT2712 and MT7622 platform to comply with the hardware design and fix MSI issue. Signed-off-by: Chuanjia Liu Acked-by: Ryder Lee Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 97 +++++++-------- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 112 ++++++++++-------- 4 files changed, 118 insertions(+), 113 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index a9cca9c146fd..de16c0d80c30 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -915,64 +915,67 @@ u3port1: usb-phy@8700 { }; }; - pcie: pcie@11700000 { + pcie1: pcie@112ff000 { compatible = "mediatek,mt2712-pcie"; device_type = "pci"; - reg = <0 0x11700000 0 0x1000>, - <0 0x112ff000 0 0x1000>; - reg-names = "port0", "port1"; + reg = <0 0x112ff000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; #address-cells = <3>; #size-cells = <2>; - interrupts = , - ; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE0>, + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; - phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1"; + clock-names = "sys_ck1", "ahb_ck1"; + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy1"; bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; + status = "disabled"; - pcie0: pcie@0,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; }; + }; - pcie1: pcie@1,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; + pcie0: pcie@11700000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, + <&pericfg CLK_PERI_PCIE0>; + clock-names = "sys_ck0", "ahb_ck0"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 2f77dc40b9b8..2b9bf8dd14ec 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -257,18 +257,16 @@ flash@0 { }; }; -&pcie { +&pcie0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; + pinctrl-0 = <&pcie0_pins>; status = "okay"; +}; - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; }; &pio { diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index f2dc850010f1..596c073d8b05 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -234,14 +234,10 @@ flash@0 { }; }; -&pcie { +&pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_pins>; status = "okay"; - - pcie@0,0 { - status = "okay"; - }; }; &pio { diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 890a942ec608..6f8cb3ad1e84 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -781,75 +781,83 @@ pciesys: pciesys@1a100800 { #reset-cells = <1>; }; - pcie: pcie@1a140000 { + pciecfg: pciecfg@1a140000 { + compatible = "mediatek,generic-pciecfg", "syscon"; + reg = <0 0x1a140000 0 0x1000>; + }; + + pcie0: pcie@1a143000 { compatible = "mediatek,mt7622-pcie"; device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, - <0 0x1a143000 0 0x1000>, - <0 0x1a145000 0 0x1000>; - reg-names = "subsys", "port0", "port1"; + reg = <0 0x1a143000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; #address-cells = <3>; #size-cells = <2>; - interrupts = , - ; + interrupts = ; + interrupt-names = "pcie_irq"; clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, <&pciesys CLK_PCIE_P0_AHB_EN>, <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; + <&pciesys CLK_PCIE_P0_PIPE_EN>; + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; status = "disabled"; - pcie0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; }; + }; - pcie1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; + pcie1: pcie@1a145000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a145000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P1_OBFF_EN>, + <&pciesys CLK_PCIE_P1_PIPE_EN>; + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; }; }; From f07c776f6d7ed5f8423863efd2445016e690aba1 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:44 +0200 Subject: [PATCH 5/9] arm64: dts: mediatek: Move reset controller constants into common location The DT binding includes for reset controllers are located in include/dt-bindings/reset/. Move the Mediatek reset constants in there. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Guenter Roeck Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20210930103105.v4.1.I514d9aafff3a062f751b37d3fea7402f67595b86@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- drivers/watchdog/mtk_wdt.c | 6 +++--- .../dt-bindings/{reset-controller => reset}/mt2712-resets.h | 0 .../dt-bindings/{reset-controller => reset}/mt8183-resets.h | 0 .../dt-bindings/{reset-controller => reset}/mt8192-resets.h | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename include/dt-bindings/{reset-controller => reset}/mt2712-resets.h (100%) rename include/dt-bindings/{reset-controller => reset}/mt8183-resets.h (100%) rename include/dt-bindings/{reset-controller => reset}/mt8192-resets.h (100%) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9ea4c5001b1e..de12f78c2ee0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 796fbb048cbe..3d208d627fb0 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,9 +9,9 @@ * Based on sunxi_wdt.c */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset/mt2712-resets.h similarity index 100% rename from include/dt-bindings/reset-controller/mt2712-resets.h rename to include/dt-bindings/reset/mt2712-resets.h diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h similarity index 100% rename from include/dt-bindings/reset-controller/mt8183-resets.h rename to include/dt-bindings/reset/mt8183-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h similarity index 100% rename from include/dt-bindings/reset-controller/mt8192-resets.h rename to include/dt-bindings/reset/mt8192-resets.h From 6046ffc3c08d48fd9b5ccf1d2a4938ae83dd2a4d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:45 +0200 Subject: [PATCH 6/9] dt-bindings: mediatek: Add #reset-cells to mmsys system controller The mmsys system controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advertise the number of cells needed to describe each of the resets. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid Signed-off-by: Matthias Brugger --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index f9ffa5b703a5..763c62323a74 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -43,6 +43,9 @@ properties: "#clock-cells": const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg @@ -56,4 +59,5 @@ examples: compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; From 858d8e140c497b6ae7f0711273d4c8d525bf9584 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:46 +0200 Subject: [PATCH 7/9] dt-bindings: display: mediatek: add dsi reset optional property Update device tree binding documentation for the dsi to add the optional property to reset the dsi controller. Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.3.Ifec72a83f224b62f24cfc967edfe78c5d276b2e3@changeid Signed-off-by: Matthias Brugger --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index d30428b9fb33..36b01458f45c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -19,6 +19,11 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached DSI panel or DSI-to-eDP encoder chip. +Optional properties: +- resets: list of phandle + reset specifier pair, as described in [1]. + +[1] Documentation/devicetree/bindings/reset/reset.txt + MIPI TX Configuration Module ============================ @@ -45,6 +50,7 @@ dsi0: dsi@1401b000 { clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; From 7fdb1bc3d96e9c8860dd434dd725cc94603744fa Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:47 +0200 Subject: [PATCH 8/9] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ include/dt-bindings/reset/mt8173-resets.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d9e005ae5bb0..dee66e5f054c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -996,6 +996,7 @@ mmsys: syscon@14000000 { assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; @@ -1222,6 +1223,7 @@ dsi0: dsi@1401b000 { <&mmsys CLK_MM_DSI0_DIGITAL>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; status = "disabled"; diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h index ba8636eda5ae..6a60c7cecc4c 100644 --- a/include/dt-bindings/reset/mt8173-resets.h +++ b/include/dt-bindings/reset/mt8173-resets.h @@ -27,6 +27,8 @@ #define MT8173_INFRA_GCE_FAXI_RST 40 #define MT8173_INFRA_MMIOMMURST 47 +/* MMSYS resets */ +#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25 /* PERICFG resets */ #define MT8173_PERI_UART0_SW_RST 0 From 4bdb00edbd2ae354471f8d37d976a864bf29b60f Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:48 +0200 Subject: [PATCH 9/9] arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0 Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. While here, also remove the undocumented and also not used 'mediatek,syscon-dsi' property. Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.5.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 ++- include/dt-bindings/reset/mt8183-resets.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index de12f78c2ee0..ba4584faca5a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1319,6 +1319,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; @@ -1433,11 +1434,11 @@ dsi0: dsi@14014000 { reg = <0 0x14014000 0 0x1000>; interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - mediatek,syscon-dsi = <&mmsys 0x140>; clocks = <&mmsys CLK_MM_DSI0_MM>, <&mmsys CLK_MM_DSI0_IF>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; }; diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h index a1bbd41e0d12..48c5d2de0a38 100644 --- a/include/dt-bindings/reset/mt8183-resets.h +++ b/include/dt-bindings/reset/mt8183-resets.h @@ -80,6 +80,9 @@ #define MT8183_INFRACFG_SW_RST_NUM 128 +/* MMSYS resets */ +#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25 + #define MT8183_TOPRGU_MM_SW_RST 1 #define MT8183_TOPRGU_MFG_SW_RST 2 #define MT8183_TOPRGU_VENC_SW_RST 3