mirror of https://github.com/torvalds/linux.git
perf vendor events riscv: Add StarFive Dubhe-80 JSON file
StarFive's Dubhe-80 supports raw event id 0x00 - 0x22. The raw events
are enabled through PMU node of DT binding. Besides raw event, add
standard RISC-V firmware events to support monitoring of firmware event.
Example of PMU DT node:
pmu {
compatible = "riscv,pmu";
riscv,raw-event-to-mhpmcounters =
/* Event ID 1-31 */
<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,
/* Event ID 32-33 */
<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,
/* Event ID 34 */
<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;
};
Example of 'perf stat' output:
[root@user]# perf stat -a \
-e access_mmu_stlb \
-e miss_mmu_stlb \
-e access_mmu_pte_c \
-e rob_flush \
-e btb_prediction_miss \
-e itlb_miss \
-e sync_del_fetch_g \
-e icache_miss \
-e bpu_br_retire \
-e bpu_br_miss \
-e ret_ins_retire \
-e ret_ins_miss \
-- openssl speed rsa2048
Doing 2048 bits private rsa's for 10s: 39 2048 bits private RSA's in
10.14s
Doing 2048 bits public rsa's for 10s: 1563 2048 bits public RSA's in
10.00s
version: 3.0.11
built on: Tue Sep 19 13:02:31 2023 UTC
options: bn(64,64)
CPUINFO: N/A
sign verify sign/s verify/s
rsa 2048 bits 0.260000s 0.006398s 3.8 156.3
Performance counter stats for 'system wide':
1338350 access_mmu_stlb
1154025 miss_mmu_stlb
1162691 access_mmu_pte_c
34067 rob_flush
11212384 btb_prediction_miss
1256242 itlb_miss
652523491 sync_del_fetch_g
384465 icache_miss
64635789 bpu_br_retire
323440 bpu_br_miss
8785143 ret_ins_retire
31236 ret_ins_miss
20.760822480 seconds time elapsed
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nikita Shubin <n.shubin@yadro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-riscv@lists.infradead.org
Link: https://lore.kernel.org/r/20231103082441.1389842-1-jisheng.teoh@starfivetech.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ji Sheng Teoh
Arnaldo Carvalho de Melo
parent
b539deafba
commit
acbf6de674
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@ -15,3 +15,4 @@
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#
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#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
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0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
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0x67e-0x80000000db000080-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
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@ -0,0 +1,172 @@
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[
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{
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"EventName": "ACCESS_MMU_STLB",
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"EventCode": "0x1",
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"BriefDescription": "access MMU STLB"
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},
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{
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"EventName": "MISS_MMU_STLB",
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"EventCode": "0x2",
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"BriefDescription": "miss MMU STLB"
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},
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{
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"EventName": "ACCESS_MMU_PTE_C",
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"EventCode": "0x3",
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"BriefDescription": "access MMU PTE-Cache"
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},
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{
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"EventName": "MISS_MMU_PTE_C",
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"EventCode": "0x4",
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"BriefDescription": "miss MMU PTE-Cache"
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},
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{
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"EventName": "ROB_FLUSH",
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"EventCode": "0x5",
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"BriefDescription": "ROB flush (all kinds of exceptions)"
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},
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{
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"EventName": "BTB_PREDICTION_MISS",
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"EventCode": "0x6",
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"BriefDescription": "BTB prediction miss"
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},
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{
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"EventName": "ITLB_MISS",
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"EventCode": "0x7",
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"BriefDescription": "ITLB miss"
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},
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{
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"EventName": "SYNC_DEL_FETCH_G",
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"EventCode": "0x8",
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"BriefDescription": "SYNC delivery a fetch-group"
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},
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{
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"EventName": "ICACHE_MISS",
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"EventCode": "0x9",
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"BriefDescription": "ICache miss"
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},
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{
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"EventName": "BPU_BR_RETIRE",
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"EventCode": "0xA",
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"BriefDescription": "condition branch instruction retire"
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},
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{
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"EventName": "BPU_BR_MISS",
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"EventCode": "0xB",
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"BriefDescription": "condition branch instruction miss"
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},
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{
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"EventName": "RET_INS_RETIRE",
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"EventCode": "0xC",
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"BriefDescription": "return instruction retire"
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},
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{
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"EventName": "RET_INS_MISS",
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"EventCode": "0xD",
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"BriefDescription": "return instruction miss"
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},
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{
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"EventName": "INDIRECT_JR_MISS",
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"EventCode": "0xE",
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"BriefDescription": "indirect JR instruction miss (inlcude without target)"
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},
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{
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"EventName": "IBUF_VAL_ID_NORDY",
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"EventCode": "0xF",
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"BriefDescription": "IBUF valid while ID not ready"
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},
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{
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"EventName": "IBUF_NOVAL_ID_RDY",
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"EventCode": "0x10",
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"BriefDescription": "IBUF not valid while ID ready"
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},
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{
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"EventName": "REN_INT_PHY_REG_NORDY",
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"EventCode": "0x11",
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"BriefDescription": "REN integer physical register file is not ready"
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},
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{
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"EventName": "REN_FP_PHY_REG_NORDY",
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"EventCode": "0x12",
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"BriefDescription": "REN floating point physical register file is not ready"
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},
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{
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"EventName": "REN_CP_NORDY",
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"EventCode": "0x13",
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"BriefDescription": "REN checkpoint is not ready"
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},
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{
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"EventName": "DEC_VAL_ROB_NORDY",
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"EventCode": "0x14",
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"BriefDescription": "DEC is valid and ROB is not ready"
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},
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{
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"EventName": "OOD_FLUSH_LS_DEP",
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"EventCode": "0x15",
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"BriefDescription": "out of order flush due to load/store dependency"
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},
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{
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"EventName": "BRU_RET_IJR_INS",
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"EventCode": "0x16",
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"BriefDescription": "BRU retire an IJR instruction"
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},
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{
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"EventName": "ACCESS_DTLB",
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"EventCode": "0x17",
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"BriefDescription": "access DTLB"
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},
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{
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"EventName": "MISS_DTLB",
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"EventCode": "0x18",
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"BriefDescription": "miss DTLB"
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},
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{
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"EventName": "LOAD_INS_DCACHE",
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"EventCode": "0x19",
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"BriefDescription": "load instruction access DCache"
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},
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{
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"EventName": "LOAD_INS_MISS_DCACHE",
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"EventCode": "0x1A",
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"BriefDescription": "load instruction miss DCache"
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},
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{
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"EventName": "STORE_INS_DCACHE",
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"EventCode": "0x1B",
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"BriefDescription": "store/amo instruction access DCache"
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},
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{
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"EventName": "STORE_INS_MISS_DCACHE",
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"EventCode": "0x1C",
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"BriefDescription": "store/amo instruction miss DCache"
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},
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{
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"EventName": "LOAD_SCACHE",
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"EventCode": "0x1D",
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"BriefDescription": "load access SCache"
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},
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{
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"EventName": "STORE_SCACHE",
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"EventCode": "0x1E",
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"BriefDescription": "store access SCache"
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},
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{
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"EventName": "LOAD_MISS_SCACHE",
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"EventCode": "0x1F",
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"BriefDescription": "load miss SCache"
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},
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{
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"EventName": "STORE_MISS_SCACHE",
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"EventCode": "0x20",
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"BriefDescription": "store miss SCache"
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},
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{
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"EventName": "L2C_PF_REQ",
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"EventCode": "0x21",
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"BriefDescription": "L2C data-prefetcher request"
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},
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{
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"EventName": "L2C_PF_HIT",
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"EventCode": "0x22",
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"BriefDescription": "L2C data-prefetcher hit"
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}
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]
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@ -0,0 +1,68 @@
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[
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{
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"ArchStdEvent": "FW_MISALIGNED_LOAD"
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},
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{
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"ArchStdEvent": "FW_MISALIGNED_STORE"
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},
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{
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"ArchStdEvent": "FW_ACCESS_LOAD"
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},
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{
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"ArchStdEvent": "FW_ACCESS_STORE"
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},
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{
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"ArchStdEvent": "FW_ILLEGAL_INSN"
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},
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{
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"ArchStdEvent": "FW_SET_TIMER"
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},
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{
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"ArchStdEvent": "FW_IPI_SENT"
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},
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{
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"ArchStdEvent": "FW_IPI_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_SENT"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_SENT"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
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}
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]
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