mirror of https://github.com/torvalds/linux.git
net: stmmac: refactor clock management in EQoS driver
Refactor clock management in EQoS driver for code reuse and to avoid redundancy. This way, only minimal changes are required when a new platform is added. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Swathi K S <swathi.ks@samsung.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250213041559.106111-1-swathi.ks@samsung.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Swathi K S
Jakub Kicinski
parent
c6287e1a85
commit
a045e40645
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@ -29,10 +29,8 @@ struct tegra_eqos {
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void __iomem *regs;
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struct reset_control *rst;
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struct clk *clk_master;
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struct clk *clk_slave;
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struct clk *clk_tx;
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struct clk *clk_rx;
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struct gpio_desc *reset;
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};
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@ -123,49 +121,14 @@ static int dwc_qos_probe(struct platform_device *pdev,
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struct plat_stmmacenet_data *plat_dat,
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struct stmmac_resources *stmmac_res)
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{
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int err;
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plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk");
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if (IS_ERR(plat_dat->stmmac_clk)) {
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dev_err(&pdev->dev, "apb_pclk clock not found.\n");
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return PTR_ERR(plat_dat->stmmac_clk);
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}
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err = clk_prepare_enable(plat_dat->stmmac_clk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n",
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err);
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return err;
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}
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plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk");
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if (IS_ERR(plat_dat->pclk)) {
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dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
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err = PTR_ERR(plat_dat->pclk);
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goto disable;
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}
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err = clk_prepare_enable(plat_dat->pclk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n",
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err);
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goto disable;
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for (int i = 0; i < plat_dat->num_clks; i++) {
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if (strcmp(plat_dat->clks[i].id, "apb_pclk") == 0)
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plat_dat->stmmac_clk = plat_dat->clks[i].clk;
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else if (strcmp(plat_dat->clks[i].id, "phy_ref_clk") == 0)
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plat_dat->pclk = plat_dat->clks[i].clk;
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}
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return 0;
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disable:
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clk_disable_unprepare(plat_dat->stmmac_clk);
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return err;
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}
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static void dwc_qos_remove(struct platform_device *pdev)
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{
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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clk_disable_unprepare(priv->plat->pclk);
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clk_disable_unprepare(priv->plat->stmmac_clk);
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}
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#define SDMEMCOMPPADCTRL 0x8800
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@ -278,52 +241,19 @@ static int tegra_eqos_probe(struct platform_device *pdev,
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if (!is_of_node(dev->fwnode))
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goto bypass_clk_reset_gpio;
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eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus");
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if (IS_ERR(eqos->clk_master)) {
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err = PTR_ERR(eqos->clk_master);
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goto error;
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for (int i = 0; i < data->num_clks; i++) {
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if (strcmp(data->clks[i].id, "slave_bus") == 0) {
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eqos->clk_slave = data->clks[i].clk;
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data->stmmac_clk = eqos->clk_slave;
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} else if (strcmp(data->clks[i].id, "tx") == 0) {
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eqos->clk_tx = data->clks[i].clk;
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}
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}
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err = clk_prepare_enable(eqos->clk_master);
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if (err < 0)
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goto error;
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eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus");
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if (IS_ERR(eqos->clk_slave)) {
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err = PTR_ERR(eqos->clk_slave);
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goto disable_master;
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}
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data->stmmac_clk = eqos->clk_slave;
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err = clk_prepare_enable(eqos->clk_slave);
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if (err < 0)
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goto disable_master;
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eqos->clk_rx = devm_clk_get(&pdev->dev, "rx");
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if (IS_ERR(eqos->clk_rx)) {
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err = PTR_ERR(eqos->clk_rx);
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goto disable_slave;
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}
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err = clk_prepare_enable(eqos->clk_rx);
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if (err < 0)
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goto disable_slave;
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eqos->clk_tx = devm_clk_get(&pdev->dev, "tx");
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if (IS_ERR(eqos->clk_tx)) {
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err = PTR_ERR(eqos->clk_tx);
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goto disable_rx;
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}
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err = clk_prepare_enable(eqos->clk_tx);
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if (err < 0)
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goto disable_rx;
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eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH);
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if (IS_ERR(eqos->reset)) {
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err = PTR_ERR(eqos->reset);
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goto disable_tx;
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return err;
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}
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usleep_range(2000, 4000);
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@ -365,15 +295,7 @@ static int tegra_eqos_probe(struct platform_device *pdev,
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reset_control_assert(eqos->rst);
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reset_phy:
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gpiod_set_value(eqos->reset, 1);
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disable_tx:
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clk_disable_unprepare(eqos->clk_tx);
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disable_rx:
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clk_disable_unprepare(eqos->clk_rx);
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disable_slave:
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clk_disable_unprepare(eqos->clk_slave);
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disable_master:
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clk_disable_unprepare(eqos->clk_master);
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error:
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return err;
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}
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@ -383,10 +305,6 @@ static void tegra_eqos_remove(struct platform_device *pdev)
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reset_control_assert(eqos->rst);
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gpiod_set_value(eqos->reset, 1);
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clk_disable_unprepare(eqos->clk_tx);
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clk_disable_unprepare(eqos->clk_rx);
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clk_disable_unprepare(eqos->clk_slave);
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clk_disable_unprepare(eqos->clk_master);
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}
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struct dwc_eth_dwmac_data {
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@ -398,7 +316,6 @@ struct dwc_eth_dwmac_data {
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static const struct dwc_eth_dwmac_data dwc_qos_data = {
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.probe = dwc_qos_probe,
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.remove = dwc_qos_remove,
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};
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static const struct dwc_eth_dwmac_data tegra_eqos_data = {
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@ -434,9 +351,19 @@ static int dwc_eth_dwmac_probe(struct platform_device *pdev)
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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ret = devm_clk_bulk_get_all(&pdev->dev, &plat_dat->clks);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "Failed to retrieve all required clocks\n");
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plat_dat->num_clks = ret;
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ret = clk_bulk_prepare_enable(plat_dat->num_clks, plat_dat->clks);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Failed to enable clocks\n");
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ret = data->probe(pdev, plat_dat, &stmmac_res);
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if (ret < 0) {
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dev_err_probe(&pdev->dev, ret, "failed to probe subdriver\n");
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clk_bulk_disable_unprepare(plat_dat->num_clks, plat_dat->clks);
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return ret;
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}
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@ -451,7 +378,8 @@ static int dwc_eth_dwmac_probe(struct platform_device *pdev)
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return ret;
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remove:
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data->remove(pdev);
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if (data->remove)
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data->remove(pdev);
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return ret;
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}
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@ -459,10 +387,15 @@ static int dwc_eth_dwmac_probe(struct platform_device *pdev)
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static void dwc_eth_dwmac_remove(struct platform_device *pdev)
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{
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const struct dwc_eth_dwmac_data *data = device_get_match_data(&pdev->dev);
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struct plat_stmmacenet_data *plat_data = dev_get_platdata(&pdev->dev);
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stmmac_dvr_remove(&pdev->dev);
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data->remove(pdev);
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if (data->remove)
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data->remove(pdev);
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if (plat_data)
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clk_bulk_disable_unprepare(plat_data->num_clks, plat_data->clks);
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}
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static const struct of_device_id dwc_eth_dwmac_match[] = {
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@ -254,6 +254,8 @@ struct plat_stmmacenet_data {
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struct clk *clk_ptp_ref;
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unsigned long clk_ptp_rate;
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unsigned long clk_ref_rate;
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struct clk_bulk_data *clks;
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int num_clks;
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unsigned int mult_fact_100ns;
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s32 ptp_max_adj;
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u32 cdc_error_adj;
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