mirror of https://github.com/torvalds/linux.git
Initial Anlogic Platform Support
Add bindings for the serial and timer peripherals, and a basic soc dtsi for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board for this SoC. Add myself as maintainer for this platform for the time being. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaR7j/AAKCRB4tDGHoIJi 0k3VAP9GQl/z1wt5KBj+Qhcvo84KW0gAUZVnHn1limK2EkB29wD+Ix8MTs3FWoRT HghtdGPQZBnrOdsuJe3lDieDt2Oxtgg= =ZLUq -----END PGP SIGNATURE----- Merge tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc Initial Anlogic Platform Support Add bindings for the serial and timer peripherals, and a basic soc dtsi for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board for this SoC. Add myself as maintainer for this platform for the time being. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
This commit is contained in:
Arnd Bergmann
commit
9b418a3bfd
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@ -0,0 +1,27 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/anlogic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Anlogic SoC-based boards
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maintainers:
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- Junhui Liu <junhui.liu@pigmoral.tech>
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description:
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Anlogic SoC-based boards
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- items:
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- enum:
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- milianke,mlkpai-fs01
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- const: anlogic,dr1v90
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additionalProperties: true
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...
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@ -48,6 +48,7 @@ properties:
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- amd,mbv64
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- andestech,ax45mp
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- canaan,k210
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- nuclei,ux900
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- sifive,bullet0
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- sifive,e5
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- sifive,e7
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@ -51,6 +51,7 @@ properties:
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- const: renesas,rzn1-uart
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- items:
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- enum:
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- anlogic,dr1v90-uart
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- brcm,bcm11351-dw-apb-uart
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- brcm,bcm21664-dw-apb-uart
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- rockchip,px30-uart
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@ -4,18 +4,23 @@
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$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo CLINT Timer
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title: ACLINT Machine-level Timer Device
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maintainers:
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- Inochi Amaoto <inochiama@outlook.com>
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properties:
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compatible:
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items:
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- enum:
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- sophgo,sg2042-aclint-mtimer
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- sophgo,sg2044-aclint-mtimer
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- const: thead,c900-aclint-mtimer
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oneOf:
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- items:
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- enum:
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- sophgo,sg2042-aclint-mtimer
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- sophgo,sg2044-aclint-mtimer
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- const: thead,c900-aclint-mtimer
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- items:
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- enum:
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- anlogic,dr1v90-aclint-mtimer
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- const: nuclei,ux900-aclint-mtimer
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reg:
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items:
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@ -132,6 +132,8 @@ patternProperties:
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description: Anbernic
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"^andestech,.*":
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description: Andes Technology Corporation
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"^anlogic,.*":
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description: Shanghai Anlogic Infotech Co., Ltd.
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"^anvo,.*":
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description: Anvo-Systems Dresden GmbH
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"^aoly,.*":
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@ -1025,6 +1027,8 @@ patternProperties:
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description: MikroElektronika d.o.o.
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"^mikrotik,.*":
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description: MikroTik
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"^milianke,.*":
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description: Changzhou Milianke Electronic Technology Co., Ltd
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"^milkv,.*":
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description: MilkV Technology Co., Ltd
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"^miniand,.*":
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@ -1142,6 +1146,8 @@ patternProperties:
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description: Novatek
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"^novtech,.*":
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description: NovTech, Inc.
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"^nuclei,.*":
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description: Nuclei System Technology
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"^numonyx,.*":
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description: Numonyx (deprecated, use micron)
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deprecated: true
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@ -22089,6 +22089,14 @@ F: Documentation/devicetree/bindings/riscv/andes.yaml
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F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
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F: arch/riscv/boot/dts/andes/
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RISC-V ANLOGIC SoC SUPPORT
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M: Conor Dooley <conor@kernel.org>
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
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L: linux-riscv@lists.infradead.org
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S: Odd Fixes
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F: Documentation/devicetree/bindings/riscv/anlogic.yaml
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F: arch/riscv/boot/dts/anlogic/
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RISC-V ARCHITECTURE
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M: Paul Walmsley <pjw@kernel.org>
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M: Palmer Dabbelt <palmer@dabbelt.com>
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@ -7,6 +7,11 @@ config ARCH_ANDES
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help
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This enables support for Andes SoC platform hardware.
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config ARCH_ANLOGIC
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bool "Anlogic SoCs"
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help
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This enables support for Anlogic SoC platform hardware.
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config ARCH_ESWIN
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bool "ESWIN SoCs"
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help
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += allwinner
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subdir-y += andes
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subdir-y += anlogic
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subdir-y += canaan
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subdir-y += eswin
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subdir-y += microchip
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*/
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#include "dr1v90.dtsi"
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/ {
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model = "Milianke MLKPAI-FS01";
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compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
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aliases {
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serial0 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x20000000>;
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};
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};
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&uart1 {
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status = "okay";
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};
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Anlogic DR1V90";
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compatible = "anlogic,dr1v90";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <800000000>;
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cpu@0 {
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compatible = "nuclei,ux900", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <256>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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reg = <0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
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"zbkc", "zbs", "zicntr", "zicsr", "zifencei",
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"zihintpause", "zihpm";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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aclint_mswi: interrupt-controller@68031000 {
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compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
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reg = <0x0 0x68031000 0x0 0x4000>;
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interrupts-extended = <&cpu0_intc 3>;
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};
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aclint_mtimer: timer@68035000 {
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compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
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reg = <0x0 0x68035000 0x0 0x8000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu0_intc 7>;
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};
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aclint_sswi: interrupt-controller@6803d000 {
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compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
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reg = <0x0 0x6803d000 0x0 0x3000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 1>;
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};
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plic: interrupt-controller@6c000000 {
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compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
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reg = <0x0 0x6c000000 0x0 0x4000000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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riscv,ndev = <150>;
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};
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uart0: serial@f8400000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8400000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <71>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@f8401000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8401000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <72>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_PROFILING=y
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CONFIG_ARCH_ANDES=y
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CONFIG_ARCH_ANLOGIC=y
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CONFIG_ARCH_MICROCHIP=y
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CONFIG_ARCH_SIFIVE=y
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CONFIG_ARCH_SOPHGO=y
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Reference in New Issue