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clocksource/drivers/timer-rtl-otto: Simplify documentation 

While the main SoC PLL is responsible for the lexra bus frequency
it has no implications on the the timer divisior. Update the
comments accordingly.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250804080328.2609287-5-markus.stockhausen@gmx.de
This commit is contained in:
Markus Stockhausen 2025-08-04 04:03:28 -04:00 committed by Daniel Lezcano
parent c445bffbf2
commit 931bd92738
1 changed files with 4 additions and 6 deletions
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10
drivers/clocksource/timer-rtl-otto.c
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@ -41,12 +41,10 @@
#define RTTM_MAX_DIVISOR GENMASK(15, 0) #define RTTM_MAX_DIVISOR GENMASK(15, 0)
/* /*
* Timers are derived from the LXB clock frequency. Usually this is a fixed * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz
* multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. * on RTL930x and 200 MHz on the other platforms. With 3.125 MHz choose a common
* Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its * divisor to have enough range and detail. This provides comparability between
* base. The only meaningful frequencies we can achieve from that are 175.000 * the different platforms.
* MHz and 153.125 MHz. The greatest common divisor of all explained possible
* speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
*/ */
#define RTTM_TICKS_PER_SEC 3125000 #define RTTM_TICKS_PER_SEC 3125000