mirror of https://github.com/torvalds/linux.git
dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support
Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC functionality but have architectural differences that require schema updates. Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and "renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to the RZ/T2H variant. The new SoCs require reset support with two reset lines for converter register reset and converter reset, which are not present on RZ/N1. Update port configurations to accommodate the different architectures. RZ/N1 supports 5 ports numbered 1-5 with complex input mappings covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports numbered 0-3 with simplified input mappings covering indices 0-8. Extend the switch port configuration property to support value 0 for the new SoCs. Add a new dt-bindings header file with media interface connection matrix constants that map GMAC, ESC, and ETHSW ports to numeric identifiers for use with RZ/T2H and RZ/N2H device trees. Update DT schema validation to ensure proper port numbering and input mappings per SoC variant. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250910204132.319975-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lad Prabhakar
Jakub Kicinski
parent
943a4fd7e1
commit
8c01cc2382
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@ -4,14 +4,15 @@
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$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/N1 MII converter
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title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter
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maintainers:
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- Clément Léger <clement.leger@bootlin.com>
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description: |
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This MII converter is present on the Renesas RZ/N1 SoC family. It is
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responsible to do MII passthrough or convert it to RMII/RGMII.
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This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC
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families. It is responsible to do MII passthrough or convert it to RMII/RGMII.
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properties:
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'#address-cells':
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@ -21,10 +22,16 @@ properties:
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const: 0
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compatible:
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items:
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- enum:
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- renesas,r9a06g032-miic
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- const: renesas,rzn1-miic
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oneOf:
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- items:
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- enum:
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- renesas,r9a06g032-miic
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- const: renesas,rzn1-miic
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- items:
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- const: renesas,r9a09g077-miic # RZ/T2H
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- items:
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- const: renesas,r9a09g087-miic # RZ/N2H
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- const: renesas,r9a09g077-miic
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reg:
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maxItems: 1
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@ -43,11 +50,22 @@ properties:
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- const: rmii_ref
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- const: hclk
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resets:
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items:
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- description: Converter register reset
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- description: Converter reset
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reset-names:
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items:
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- const: rst
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- const: crst
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renesas,miic-switch-portin:
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description: MII Switch PORTIN configuration. This value should use one of
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the values defined in dt-bindings/net/pcs-rzn1-miic.h.
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the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC and
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include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2]
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enum: [0, 1, 2]
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power-domains:
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maxItems: 1
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@ -60,11 +78,12 @@ patternProperties:
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properties:
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reg:
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description: MII Converter port number.
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enum: [1, 2, 3, 4, 5]
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enum: [0, 1, 2, 3, 4, 5]
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renesas,miic-input:
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description: Converter input port configuration. This value should use
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one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
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one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC
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and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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@ -73,47 +92,109 @@ patternProperties:
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additionalProperties: false
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allOf:
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- if:
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,rzn1-miic
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then:
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properties:
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renesas,miic-switch-portin:
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enum: [1, 2]
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resets: false
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reset-names: false
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patternProperties:
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"^mii-conv@[0-5]$":
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properties:
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reg:
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const: 1
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then:
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properties:
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renesas,miic-input:
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const: 0
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- if:
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enum: [1, 2, 3, 4, 5]
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allOf:
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- if:
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properties:
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reg:
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const: 1
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then:
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properties:
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renesas,miic-input:
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const: 0
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- if:
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properties:
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reg:
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const: 2
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then:
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properties:
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renesas,miic-input:
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enum: [1, 11]
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- if:
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properties:
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reg:
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const: 3
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then:
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properties:
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renesas,miic-input:
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enum: [7, 10]
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- if:
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properties:
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reg:
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const: 4
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then:
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properties:
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renesas,miic-input:
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enum: [4, 6, 9, 13]
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- if:
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properties:
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reg:
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const: 5
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then:
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properties:
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renesas,miic-input:
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enum: [3, 5, 8, 12]
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else:
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properties:
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renesas,miic-switch-portin:
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const: 0
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required:
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- resets
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- reset-names
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patternProperties:
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"^mii-conv@[0-5]$":
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properties:
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reg:
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const: 2
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then:
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properties:
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renesas,miic-input:
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enum: [1, 11]
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- if:
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properties:
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reg:
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const: 3
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then:
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properties:
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renesas,miic-input:
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enum: [7, 10]
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- if:
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properties:
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reg:
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const: 4
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then:
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properties:
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renesas,miic-input:
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enum: [4, 6, 9, 13]
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- if:
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properties:
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reg:
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const: 5
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then:
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properties:
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renesas,miic-input:
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enum: [3, 5, 8, 12]
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enum: [0, 1, 2, 3]
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allOf:
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- if:
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properties:
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reg:
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const: 0
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then:
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properties:
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renesas,miic-input:
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enum: [0, 3, 6]
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- if:
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properties:
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reg:
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const: 1
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then:
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properties:
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renesas,miic-input:
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enum: [1, 4, 7]
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- if:
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properties:
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reg:
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const: 2
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then:
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properties:
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renesas,miic-input:
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enum: [2, 5, 8]
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- if:
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properties:
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reg:
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const: 3
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then:
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properties:
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renesas,miic-input:
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const: 1
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required:
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- '#address-cells'
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2025 Renesas Electronics Corporation.
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*/
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#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
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#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
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/*
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* Media Interface Connection Matrix
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* ===========================================================
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*
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* Selects the function of the Media interface of the MAC to be used
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*
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* SW_MODE[2:0] | Port 0 | Port 1 | Port 2 | Port 3
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* -------------|-------------|-------------|-------------|-------------
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* 000b | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1
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* 001b | ESC Port0 | ESC Port1 | GMAC2 | GMAC1
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* 010b | ESC Port0 | ESC Port1 | ETHSW Port2 | GMAC1
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* 011b | ESC Port0 | ESC Port1 | ESC Port2 | GMAC1
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* 100b | ETHSW Port0 | ESC Port1 | ESC Port2 | GMAC1
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* 101b | ETHSW Port0 | ESC Port1 | ETHSW Port2 | GMAC1
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* 110b | ETHSW Port0 | ETHSW Port1 | GMAC2 | GMAC1
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* 111b | GMAC0 | GMAC1 | GMAC2 | -
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*/
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#define ETHSS_GMAC0_PORT 0
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#define ETHSS_GMAC1_PORT 1
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#define ETHSS_GMAC2_PORT 2
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#define ETHSS_ESC_PORT0 3
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#define ETHSS_ESC_PORT1 4
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#define ETHSS_ESC_PORT2 5
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#define ETHSS_ETHSW_PORT0 6
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#define ETHSS_ETHSW_PORT1 7
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#define ETHSS_ETHSW_PORT2 8
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#endif
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