mirror of https://github.com/torvalds/linux.git
ASoC: mediatek: mt8189: add common header
Add header files for register definitions and structures. Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com> Link: https://patch.msgid.link/20251031073216.8662-2-Cyril.Chao@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cyril Chao
Mark Brown
parent
0140fc1189
commit
81f8f29a48
|
|
@ -0,0 +1,240 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* mt8189-afe-common.h -- Mediatek 8189 audio driver definitions
|
||||
*
|
||||
* Copyright (c) 2025 MediaTek Inc.
|
||||
* Author: Darren Ye <darren.ye@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT_8189_AFE_COMMON_H_
|
||||
#define _MT_8189_AFE_COMMON_H_
|
||||
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <sound/soc.h>
|
||||
|
||||
#include "mt8189-reg.h"
|
||||
#include "../common/mtk-base-afe.h"
|
||||
|
||||
enum {
|
||||
MTK_AFE_RATE_8K,
|
||||
MTK_AFE_RATE_11K,
|
||||
MTK_AFE_RATE_12K,
|
||||
MTK_AFE_RATE_384K,
|
||||
MTK_AFE_RATE_16K,
|
||||
MTK_AFE_RATE_22K,
|
||||
MTK_AFE_RATE_24K,
|
||||
MTK_AFE_RATE_352K,
|
||||
MTK_AFE_RATE_32K,
|
||||
MTK_AFE_RATE_44K,
|
||||
MTK_AFE_RATE_48K,
|
||||
MTK_AFE_RATE_88K,
|
||||
MTK_AFE_RATE_96K,
|
||||
MTK_AFE_RATE_176K,
|
||||
MTK_AFE_RATE_192K,
|
||||
MTK_AFE_RATE_260K,
|
||||
};
|
||||
|
||||
/* HW IPM 2.0 */
|
||||
enum {
|
||||
MTK_AFE_IPM2P0_RATE_8K = 0x0,
|
||||
MTK_AFE_IPM2P0_RATE_11K = 0x1,
|
||||
MTK_AFE_IPM2P0_RATE_12K = 0x2,
|
||||
MTK_AFE_IPM2P0_RATE_16K = 0x4,
|
||||
MTK_AFE_IPM2P0_RATE_22K = 0x5,
|
||||
MTK_AFE_IPM2P0_RATE_24K = 0x6,
|
||||
MTK_AFE_IPM2P0_RATE_32K = 0x8,
|
||||
MTK_AFE_IPM2P0_RATE_44K = 0x9,
|
||||
MTK_AFE_IPM2P0_RATE_48K = 0xa,
|
||||
MTK_AFE_IPM2P0_RATE_88K = 0xd,
|
||||
MTK_AFE_IPM2P0_RATE_96K = 0xe,
|
||||
MTK_AFE_IPM2P0_RATE_176K = 0x11,
|
||||
MTK_AFE_IPM2P0_RATE_192K = 0x12,
|
||||
MTK_AFE_IPM2P0_RATE_352K = 0x15,
|
||||
MTK_AFE_IPM2P0_RATE_384K = 0x16,
|
||||
};
|
||||
|
||||
enum {
|
||||
MTK_AFE_DAI_MEMIF_RATE_8K,
|
||||
MTK_AFE_DAI_MEMIF_RATE_16K,
|
||||
MTK_AFE_DAI_MEMIF_RATE_32K,
|
||||
MTK_AFE_DAI_MEMIF_RATE_48K,
|
||||
};
|
||||
|
||||
enum {
|
||||
MTK_AFE_PCM_RATE_8K,
|
||||
MTK_AFE_PCM_RATE_16K,
|
||||
MTK_AFE_PCM_RATE_32K,
|
||||
MTK_AFE_PCM_RATE_48K,
|
||||
};
|
||||
|
||||
enum {
|
||||
MTKAIF_PROTOCOL_1,
|
||||
MTKAIF_PROTOCOL_2,
|
||||
MTKAIF_PROTOCOL_2_CLK_P2,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8189_MEMIF_DL0,
|
||||
MT8189_MEMIF_DL1,
|
||||
MT8189_MEMIF_DL2,
|
||||
MT8189_MEMIF_DL3,
|
||||
MT8189_MEMIF_DL4,
|
||||
MT8189_MEMIF_DL5,
|
||||
MT8189_MEMIF_DL6,
|
||||
MT8189_MEMIF_DL7,
|
||||
MT8189_MEMIF_DL8,
|
||||
MT8189_MEMIF_DL23,
|
||||
MT8189_MEMIF_DL24,
|
||||
MT8189_MEMIF_DL25,
|
||||
MT8189_MEMIF_DL_24CH,
|
||||
MT8189_MEMIF_VUL0,
|
||||
MT8189_MEMIF_VUL1,
|
||||
MT8189_MEMIF_VUL2,
|
||||
MT8189_MEMIF_VUL3,
|
||||
MT8189_MEMIF_VUL4,
|
||||
MT8189_MEMIF_VUL5,
|
||||
MT8189_MEMIF_VUL6,
|
||||
MT8189_MEMIF_VUL7,
|
||||
MT8189_MEMIF_VUL8,
|
||||
MT8189_MEMIF_VUL9,
|
||||
MT8189_MEMIF_VUL10,
|
||||
MT8189_MEMIF_VUL24,
|
||||
MT8189_MEMIF_VUL25,
|
||||
MT8189_MEMIF_VUL_CM0,
|
||||
MT8189_MEMIF_VUL_CM1,
|
||||
MT8189_MEMIF_ETDM_IN0,
|
||||
MT8189_MEMIF_ETDM_IN1,
|
||||
MT8189_MEMIF_HDMI,
|
||||
MT8189_MEMIF_NUM,
|
||||
MT8189_DAI_ADDA = MT8189_MEMIF_NUM,
|
||||
MT8189_DAI_ADDA_CH34,
|
||||
MT8189_DAI_ADDA_CH56,
|
||||
MT8189_DAI_AP_DMIC,
|
||||
MT8189_DAI_AP_DMIC_CH34,
|
||||
MT8189_DAI_I2S_IN0,
|
||||
MT8189_DAI_I2S_IN1,
|
||||
MT8189_DAI_I2S_OUT0,
|
||||
MT8189_DAI_I2S_OUT1,
|
||||
MT8189_DAI_I2S_OUT4,
|
||||
MT8189_DAI_PCM_0,
|
||||
MT8189_DAI_TDM,
|
||||
MT8189_DAI_TDM_DPTX,
|
||||
MT8189_DAI_NUM,
|
||||
};
|
||||
|
||||
/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
|
||||
enum {
|
||||
MT8189_IRQ_0,
|
||||
MT8189_IRQ_1,
|
||||
MT8189_IRQ_2,
|
||||
MT8189_IRQ_3,
|
||||
MT8189_IRQ_4,
|
||||
MT8189_IRQ_5,
|
||||
MT8189_IRQ_6,
|
||||
MT8189_IRQ_7,
|
||||
MT8189_IRQ_8,
|
||||
MT8189_IRQ_9,
|
||||
MT8189_IRQ_10,
|
||||
MT8189_IRQ_11,
|
||||
MT8189_IRQ_12,
|
||||
MT8189_IRQ_13,
|
||||
MT8189_IRQ_14,
|
||||
MT8189_IRQ_15,
|
||||
MT8189_IRQ_16,
|
||||
MT8189_IRQ_17,
|
||||
MT8189_IRQ_18,
|
||||
MT8189_IRQ_19,
|
||||
MT8189_IRQ_20,
|
||||
MT8189_IRQ_21,
|
||||
MT8189_IRQ_22,
|
||||
MT8189_IRQ_23,
|
||||
MT8189_IRQ_24,
|
||||
MT8189_IRQ_25,
|
||||
MT8189_IRQ_26,
|
||||
MT8189_IRQ_31,
|
||||
MT8189_IRQ_NUM,
|
||||
};
|
||||
|
||||
/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
|
||||
enum {
|
||||
MT8189_CUS_IRQ_TDM, /* used only for TDM */
|
||||
MT8189_CUS_IRQ_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
/* AUDIO_ENGEN_CON0 */
|
||||
MT8189_AUDIO_26M_EN_ON,
|
||||
MT8189_AUDIO_F3P25M_EN_ON,
|
||||
MT8189_AUDIO_APLL1_EN_ON,
|
||||
MT8189_AUDIO_APLL2_EN_ON,
|
||||
MT8189_AUDIO_F26M_EN_RST,
|
||||
MT8189_MULTI_USER_RST,
|
||||
MT8189_MULTI_USER_BYPASS,
|
||||
/* AUDIO_TOP_CON4 */
|
||||
MT8189_CG_AUDIO_HOPPING_CK,
|
||||
MT8189_CG_AUDIO_F26M_CK,
|
||||
MT8189_CG_APLL1_CK,
|
||||
MT8189_CG_APLL2_CK,
|
||||
MT8189_PDN_APLL_TUNER2,
|
||||
MT8189_PDN_APLL_TUNER1,
|
||||
MT8189_AUDIO_CG_NUM,
|
||||
};
|
||||
|
||||
/* MCLK */
|
||||
enum {
|
||||
MT8189_I2SIN0_MCK,
|
||||
MT8189_I2SIN1_MCK,
|
||||
MT8189_I2SOUT0_MCK,
|
||||
MT8189_I2SOUT1_MCK,
|
||||
MT8189_FMI2S_MCK,
|
||||
MT8189_TDMOUT_MCK,
|
||||
MT8189_TDMOUT_BCK,
|
||||
MT8189_MCK_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
CM0,
|
||||
CM1,
|
||||
CM_NUM,
|
||||
};
|
||||
|
||||
struct clk;
|
||||
|
||||
struct mt8189_afe_private {
|
||||
struct clk **clk;
|
||||
struct regmap *pmic_regmap;
|
||||
|
||||
/* dai */
|
||||
void *dai_priv[MT8189_DAI_NUM];
|
||||
|
||||
/* adda */
|
||||
int mtkaif_protocol;
|
||||
int mtkaif_chosen_phase[4];
|
||||
int mtkaif_phase_cycle[4];
|
||||
int mtkaif_calibration_num_phase;
|
||||
int mtkaif_dmic;
|
||||
int mtkaif_dmic_ch34;
|
||||
|
||||
/* add for vs1 voter */
|
||||
bool is_adda_dl_on;
|
||||
bool is_adda_ul_on;
|
||||
/* adda dl vol idx is at maximum */
|
||||
bool is_adda_dl_max_vol;
|
||||
/* current vote status of vs1 */
|
||||
bool is_mt6363_vote;
|
||||
|
||||
/* mck */
|
||||
int mck_rate[MT8189_MCK_NUM];
|
||||
|
||||
/* channel merge */
|
||||
unsigned int cm_rate[CM_NUM];
|
||||
unsigned int cm_channels;
|
||||
};
|
||||
|
||||
int mt8189_dai_adda_register(struct mtk_base_afe *afe);
|
||||
int mt8189_dai_i2s_register(struct mtk_base_afe *afe);
|
||||
int mt8189_dai_pcm_register(struct mtk_base_afe *afe);
|
||||
int mt8189_dai_tdm_register(struct mtk_base_afe *afe);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Mediatek MT8189 audio driver interconnection definition
|
||||
*
|
||||
* Copyright (c) 2025 MediaTek Inc.
|
||||
* Author: Darren Ye <darren.ye@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8189_INTERCONNECTION_H_
|
||||
#define _MT8189_INTERCONNECTION_H_
|
||||
|
||||
/* in port define */
|
||||
#define I_CONNSYS_I2S_CH1 0
|
||||
#define I_CONNSYS_I2S_CH2 1
|
||||
#define I_GAIN0_OUT_CH1 6
|
||||
#define I_GAIN0_OUT_CH2 7
|
||||
#define I_GAIN1_OUT_CH1 8
|
||||
#define I_GAIN1_OUT_CH2 9
|
||||
#define I_GAIN2_OUT_CH1 10
|
||||
#define I_GAIN2_OUT_CH2 11
|
||||
#define I_GAIN3_OUT_CH1 12
|
||||
#define I_GAIN3_OUT_CH2 13
|
||||
#define I_STF_CH1 14
|
||||
#define I_ADDA_UL_CH1 16
|
||||
#define I_ADDA_UL_CH2 17
|
||||
#define I_ADDA_UL_CH3 18
|
||||
#define I_ADDA_UL_CH4 19
|
||||
#define I_UL_PROX_CH1 20
|
||||
#define I_UL_PROX_CH2 21
|
||||
#define I_ADDA_UL_CH5 24
|
||||
#define I_ADDA_UL_CH6 25
|
||||
#define I_DMIC0_CH1 28
|
||||
#define I_DMIC0_CH2 29
|
||||
#define I_DMIC1_CH1 30
|
||||
#define I_DMIC1_CH2 31
|
||||
|
||||
/* in port define >= 32 */
|
||||
#define I_32_OFFSET 32
|
||||
#define I_DL0_CH1 (32 - I_32_OFFSET)
|
||||
#define I_DL0_CH2 (33 - I_32_OFFSET)
|
||||
#define I_DL1_CH1 (34 - I_32_OFFSET)
|
||||
#define I_DL1_CH2 (35 - I_32_OFFSET)
|
||||
#define I_DL2_CH1 (36 - I_32_OFFSET)
|
||||
#define I_DL2_CH2 (37 - I_32_OFFSET)
|
||||
#define I_DL3_CH1 (38 - I_32_OFFSET)
|
||||
#define I_DL3_CH2 (39 - I_32_OFFSET)
|
||||
#define I_DL4_CH1 (40 - I_32_OFFSET)
|
||||
#define I_DL4_CH2 (41 - I_32_OFFSET)
|
||||
#define I_DL5_CH1 (42 - I_32_OFFSET)
|
||||
#define I_DL5_CH2 (43 - I_32_OFFSET)
|
||||
#define I_DL6_CH1 (44 - I_32_OFFSET)
|
||||
#define I_DL6_CH2 (45 - I_32_OFFSET)
|
||||
#define I_DL7_CH1 (46 - I_32_OFFSET)
|
||||
#define I_DL7_CH2 (47 - I_32_OFFSET)
|
||||
#define I_DL8_CH1 (48 - I_32_OFFSET)
|
||||
#define I_DL8_CH2 (49 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH1 (54 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH2 (55 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH3 (56 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH4 (57 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH5 (58 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH6 (59 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH7 (60 - I_32_OFFSET)
|
||||
#define I_DL_24CH_CH8 (61 - I_32_OFFSET)
|
||||
|
||||
/* in port define >= 64 */
|
||||
#define I_64_OFFSET 64
|
||||
#define I_DL23_CH1 (78 - I_64_OFFSET)
|
||||
#define I_DL23_CH2 (79 - I_64_OFFSET)
|
||||
#define I_DL24_CH1 (80 - I_64_OFFSET)
|
||||
#define I_DL24_CH2 (81 - I_64_OFFSET)
|
||||
#define I_DL25_CH1 (82 - I_64_OFFSET)
|
||||
#define I_DL25_CH2 (83 - I_64_OFFSET)
|
||||
|
||||
/* in port define >= 128 */
|
||||
#define I_128_OFFSET 128
|
||||
#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET)
|
||||
#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET)
|
||||
#define I_I2SIN0_CH1 (134 - I_128_OFFSET)
|
||||
#define I_I2SIN0_CH2 (135 - I_128_OFFSET)
|
||||
#define I_I2SIN1_CH1 (136 - I_128_OFFSET)
|
||||
#define I_I2SIN1_CH2 (137 - I_128_OFFSET)
|
||||
|
||||
/* in port define >= 192 */
|
||||
#define I_192_OFFSET 192
|
||||
#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET)
|
||||
#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET)
|
||||
#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET)
|
||||
#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET)
|
||||
#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET)
|
||||
#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET)
|
||||
#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET)
|
||||
#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET)
|
||||
#define I_SRC_4_OUT_CH1 (206 - I_192_OFFSET)
|
||||
#define I_SRC_4_OUT_CH2 (207 - I_192_OFFSET)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue