mirror of https://github.com/torvalds/linux.git
x86/mce: Separate global and per-CPU quirks
Many quirks are global configuration settings and a handful apply to each CPU. Move the per-CPU quirks to vendor init to execute them on each online CPU. Set the global quirks during BSP-only init so they're only executed once and early. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Tested-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com
This commit is contained in:
Yazen Ghannam
Borislav Petkov (AMD)
parent
a46b2bbe1e
commit
7eee1e9268
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@ -646,6 +646,28 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
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wrmsrq(MSR_K7_HWCR, hwcr);
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}
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static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c)
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{
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struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
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/* This should be disabled by the BIOS, but isn't always */
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if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
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/*
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* disable GART TBL walk error reporting, which
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* trips off incorrectly with the IOMMU & 3ware
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* & Cerberus:
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*/
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clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
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}
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/*
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* Various K7s with broken bank 0 around. Always disable
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* by default.
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*/
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if (c->x86 == 6 && this_cpu_read(mce_num_banks))
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mce_banks[0].ctl = 0;
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}
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/* cpu init entry point, called from mce.c with preempt off */
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void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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@ -653,6 +675,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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u32 low = 0, high = 0, address = 0;
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int offset = -1;
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amd_apply_cpu_quirks(c);
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mce_flags.amd_threshold = 1;
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for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
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@ -1807,8 +1807,9 @@ static void __mcheck_cpu_mce_banks_init(void)
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struct mce_bank *b = &mce_banks[i];
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/*
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* Init them all, __mcheck_cpu_apply_quirks() is going to apply
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* the required vendor quirks before
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* Init them all by default.
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*
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* The required vendor quirks will be applied before
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* __mcheck_cpu_init_prepare_banks() does the final bank setup.
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*/
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b->ctl = -1ULL;
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@ -1880,20 +1881,8 @@ static void __mcheck_cpu_init_prepare_banks(void)
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}
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}
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static void apply_quirks_amd(struct cpuinfo_x86 *c)
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static void amd_apply_global_quirks(struct cpuinfo_x86 *c)
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{
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struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
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/* This should be disabled by the BIOS, but isn't always */
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if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
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/*
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* disable GART TBL walk error reporting, which
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* trips off incorrectly with the IOMMU & 3ware
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* & Cerberus:
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*/
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clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
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}
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if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
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/*
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* Lots of broken BIOS around that don't clear them
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@ -1902,13 +1891,6 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c)
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mca_cfg.bootlog = 0;
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}
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/*
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* Various K7s with broken bank 0 around. Always disable
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* by default.
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*/
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if (c->x86 == 6 && this_cpu_read(mce_num_banks))
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mce_banks[0].ctl = 0;
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/*
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* overflow_recov is supported for F15h Models 00h-0fh
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* even though we don't have a CPUID bit for it.
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@ -1920,25 +1902,12 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c)
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mce_flags.zen_ifu_quirk = 1;
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}
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static void apply_quirks_intel(struct cpuinfo_x86 *c)
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static void intel_apply_global_quirks(struct cpuinfo_x86 *c)
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{
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struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
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/* Older CPUs (prior to family 6) don't need quirks. */
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if (c->x86_vfm < INTEL_PENTIUM_PRO)
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return;
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/*
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* SDM documents that on family 6 bank 0 should not be written
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* because it aliases to another special BIOS controlled
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* register.
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* But it's not aliased anymore on model 0x1a+
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* Don't ignore bank 0 completely because there could be a
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* valid event later, merely don't write CTL0.
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*/
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if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks))
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mce_banks[0].init = false;
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/*
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* All newer Intel systems support MCE broadcasting. Enable
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* synchronization with a one second timeout.
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@ -1964,7 +1933,7 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c)
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mce_flags.skx_repmov_quirk = 1;
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}
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static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
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static void zhaoxin_apply_global_quirks(struct cpuinfo_x86 *c)
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{
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/*
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* All newer Zhaoxin CPUs support MCE broadcasting. Enable
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@ -1976,29 +1945,6 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
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}
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}
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/* Add per CPU specific workarounds here */
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static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
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{
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struct mca_config *cfg = &mca_cfg;
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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apply_quirks_amd(c);
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break;
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case X86_VENDOR_INTEL:
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apply_quirks_intel(c);
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break;
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case X86_VENDOR_ZHAOXIN:
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apply_quirks_zhaoxin(c);
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break;
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}
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if (cfg->monarch_timeout < 0)
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cfg->monarch_timeout = 0;
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if (cfg->bootlog != 0)
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cfg->panic_timeout = 30;
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}
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static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
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{
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if (c->x86 != 5)
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@ -2256,6 +2202,23 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
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if (cap & MCG_SER_P)
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mca_cfg.ser = 1;
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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amd_apply_global_quirks(c);
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break;
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case X86_VENDOR_INTEL:
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intel_apply_global_quirks(c);
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break;
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case X86_VENDOR_ZHAOXIN:
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zhaoxin_apply_global_quirks(c);
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break;
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}
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if (mca_cfg.monarch_timeout < 0)
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mca_cfg.monarch_timeout = 0;
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if (mca_cfg.bootlog != 0)
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mca_cfg.panic_timeout = 30;
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}
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/*
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@ -2275,8 +2238,6 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
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__mcheck_cpu_cap_init();
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__mcheck_cpu_apply_quirks(c);
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if (!mce_gen_pool_init()) {
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mca_cfg.disabled = 1;
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pr_emerg("Couldn't allocate MCE records pool!\n");
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@ -468,8 +468,26 @@ static void intel_imc_init(struct cpuinfo_x86 *c)
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}
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}
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static void intel_apply_cpu_quirks(struct cpuinfo_x86 *c)
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{
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/*
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* SDM documents that on family 6 bank 0 should not be written
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* because it aliases to another special BIOS controlled
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* register.
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* But it's not aliased anymore on model 0x1a+
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* Don't ignore bank 0 completely because there could be a
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* valid event later, merely don't write CTL0.
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*
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* Older CPUs (prior to family 6) can't reach this point and already
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* return early due to the check of __mcheck_cpu_ancient_init().
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*/
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if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks))
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this_cpu_ptr(mce_banks_array)[0].init = false;
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}
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void mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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intel_apply_cpu_quirks(c);
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intel_init_cmci();
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intel_init_lmce();
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intel_imc_init(c);
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