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mmc: sdhci-of-dwcmshc: reduce CIT for better performance 

CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
hardware queue, and CMD13 can only query one slot at a time for data
transmission, which cannot be processed in parallel. Modifying the
CMD13 query interval can increase the query frequency and improve
random write performance.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Shawn Lin 2025-11-26 07:26:40 +08:00 committed by Ulf Hansson
parent c7ce6453b7
commit 79cf71c0b1
2 changed files with 6 additions and 0 deletions
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1
drivers/mmc/host/cqhci.h
View File

@ -93,6 +93,7 @@
/* send status config 1 */
#define CQHCI_SSC1 0x40
#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
#define CQHCI_SSC1_CIT_MASK GENMASK(15, 0)
/* send status config 2 */
#define CQHCI_SSC2 0x44

5
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@ -644,6 +644,11 @@ static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
u32 reg;
/* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
reg |= CQHCI_ENABLE;
sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);