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x86/microcode/intel: Establish staging control logic 

When microcode staging is initiated, operations are carried out through
an MMIO interface. Each package has a unique interface specified by the
IA32_MCU_STAGING_MBOX_ADDR MSR, which maps to a set of 32-bit registers.

Prepare staging with the following steps:

  1.  Ensure the microcode image is 32-bit aligned to match the MMIO
      register size.

  2.  Identify each MMIO interface based on its per-package scope.

  3.  Invoke the staging function for each identified interface, which
      will be implemented separately.

  [ bp: Improve error logging. ]

Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Anselm Busse <abusse@amazon.de>
Link: https://lore.kernel.org/all/871pznq229.ffs@tglx
This commit is contained in:
Chang S. Bae 2025-09-21 15:48:37 -07:00 committed by Borislav Petkov (AMD)
parent 7cdda85ed9
commit 740144bc6b
2 changed files with 53 additions and 0 deletions
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2
arch/x86/include/asm/msr-index.h
View File

@ -1226,6 +1226,8 @@
#define MSR_IA32_VMX_VMFUNC 0x00000491
#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5
/* Resctrl MSRs: */
/* - Intel: */
#define MSR_IA32_L3_QOS_CFG 0xc81

51
arch/x86/kernel/cpu/microcode/intel.c
View File

@ -299,6 +299,56 @@ static __init struct microcode_intel *scan_microcode(void *data, size_t size,
return size ? NULL : patch;
}
/*
* Handle the staging process using the mailbox MMIO interface.
* Return 0 on success or an error code on failure.
*/
static int do_stage(u64 mmio_pa)
{
pr_debug_once("Staging implementation is pending.\n");
return -EPROTONOSUPPORT;
}
static void stage_microcode(void)
{
unsigned int pkg_id = UINT_MAX;
int cpu, err;
u64 mmio_pa;
if (!IS_ALIGNED(get_totalsize(&ucode_patch_late->hdr), sizeof(u32))) {
pr_err("Microcode image 32-bit misaligned (0x%x), staging failed.\n",
get_totalsize(&ucode_patch_late->hdr));
return;
}
lockdep_assert_cpus_held();
/*
* The MMIO address is unique per package, and all the SMT
* primary threads are online here. Find each MMIO space by
* their package IDs to avoid duplicate staging.
*/
for_each_cpu(cpu, cpu_primary_thread_mask) {
if (topology_logical_package_id(cpu) == pkg_id)
continue;
pkg_id = topology_logical_package_id(cpu);
err = rdmsrq_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa);
if (WARN_ON_ONCE(err))
return;
err = do_stage(mmio_pa);
if (err) {
pr_err("Error: staging failed (%d) for CPU%d at package %u.\n",
err, cpu, pkg_id);
return;
}
}
pr_info("Staging of patch revision 0x%x succeeded.\n", ucode_patch_late->hdr.rev);
}
static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
struct microcode_intel *mc,
u32 *cur_rev)
@ -627,6 +677,7 @@ static struct microcode_ops microcode_intel_ops = {
.collect_cpu_info = collect_cpu_info,
.apply_microcode = apply_microcode_late,
.finalize_late_load = finalize_late_load,
.stage_microcode = stage_microcode,
.use_nmi = IS_ENABLED(CONFIG_X86_64),
};