mirror of https://github.com/torvalds/linux.git
Merge branch 'for-6.19/nintendo' into for-linus
- switch to WQ_PERCPU workaueues (Marco Crivellari) - reduce potential initialization blocking time of hid-nintendo (Willy Huang)
This commit is contained in:
Jiri Kosina
commit
7362b5b493
2
.mailmap
2
.mailmap
|
|
@ -227,6 +227,7 @@ Dmitry Safonov <0x7f454c46@gmail.com> <dima@arista.com>
|
|||
Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
|
||||
Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
|
||||
Domen Puncer <domen@coderock.org>
|
||||
Dong Aisheng <aisheng.dong@nxp.com> <b29396@freescale.com>
|
||||
Douglas Gilbert <dougg@torque.net>
|
||||
Drew Fustini <fustini@kernel.org> <drew@pdp7.com>
|
||||
<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
|
||||
|
|
@ -803,6 +804,7 @@ Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko.ursulin@onelan.co.uk>
|
|||
Tvrtko Ursulin <tursulin@ursulin.net> <tvrtko@ursulin.net>
|
||||
Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>
|
||||
Tzung-Bi Shih <tzungbi@kernel.org> <tzungbi@google.com>
|
||||
Umang Jain <uajain@igalia.com> <umang.jain@ideasonboard.com>
|
||||
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
|
||||
Uwe Kleine-König <u.kleine-koenig@baylibre.com> <ukleinek@baylibre.com>
|
||||
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
|
|
|
|||
5
CREDITS
5
CREDITS
|
|
@ -1890,6 +1890,11 @@ S: Reading
|
|||
S: RG6 2NU
|
||||
S: United Kingdom
|
||||
|
||||
N: Michael Jamet
|
||||
E: michael.jamet@intel.com
|
||||
D: Thunderbolt/USB4 driver maintainer
|
||||
D: Thunderbolt/USB4 networking driver maintainer
|
||||
|
||||
N: Dave Jeffery
|
||||
E: dhjeffery@gmail.com
|
||||
D: SCSI hacks and IBM ServeRAID RAID driver maintenance
|
||||
|
|
|
|||
|
|
@ -23,3 +23,9 @@ Contact: Longfang Liu <liulongfang@huawei.com>
|
|||
Description: Read the live migration status of the vfio device.
|
||||
The contents of the state file reflects the migration state
|
||||
relative to those defined in the vfio_device_mig_state enum
|
||||
|
||||
What: /sys/kernel/debug/vfio/<device>/migration/features
|
||||
Date: Oct 2025
|
||||
KernelVersion: 6.18
|
||||
Contact: Cédric Le Goater <clg@redhat.com>
|
||||
Description: Read the migration features of the vfio device.
|
||||
|
|
|
|||
|
|
@ -239,3 +239,9 @@ Date: March 2020
|
|||
KernelVersion: 5.7
|
||||
Contact: Mike Leach or Mathieu Poirier
|
||||
Description: (Write) Clear all channel / trigger programming.
|
||||
|
||||
What: /sys/bus/coresight/devices/<cti-name>/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -13,3 +13,9 @@ KernelVersion: 6.14
|
|||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (R) Show the trace ID that will appear in the trace stream
|
||||
coming from this trace entity.
|
||||
|
||||
What: /sys/bus/coresight/devices/dummy_source<N>/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -19,6 +19,12 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
|
|||
into the Trace RAM following the trigger event is equal to the
|
||||
value stored in this register+1 (from ARM ETB-TRM).
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.etb/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
|
||||
Date: March 2016
|
||||
KernelVersion: 4.7
|
||||
|
|
|
|||
|
|
@ -251,6 +251,12 @@ KernelVersion: 4.4
|
|||
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
Description: (RO) Holds the cpu number this tracer is affined to.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
|
||||
Date: September 2015
|
||||
KernelVersion: 4.4
|
||||
|
|
|
|||
|
|
@ -329,6 +329,12 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
|||
Description: (RW) Access the selected single show PE comparator control
|
||||
register.
|
||||
|
||||
What: /sys/bus/coresight/devices/etm<N>/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
||||
What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
|
||||
Date: April 2015
|
||||
KernelVersion: 4.01
|
||||
|
|
|
|||
|
|
@ -10,3 +10,9 @@ Date: November 2014
|
|||
KernelVersion: 3.19
|
||||
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
Description: (RW) Defines input port priority order.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.funnel/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -51,3 +51,9 @@ KernelVersion: 4.7
|
|||
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
Description: (RW) Holds the trace ID that will appear in the trace stream
|
||||
coming from this trace entity.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.stm/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -107,3 +107,9 @@ Contact: Anshuman Khandual <anshuman.khandual@arm.com>
|
|||
Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
|
||||
only provide a mode which is supported for a given ETR device. This
|
||||
file is available only for TMC ETR devices.
|
||||
|
||||
What: /sys/bus/coresight/devices/<memory_map>.tmc/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -272,3 +272,9 @@ KernelVersion 6.15
|
|||
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
|
||||
Description:
|
||||
(RW) Set/Get the enablement of the individual lane.
|
||||
|
||||
What: /sys/bus/coresight/devices/<tpdm-name>/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -12,3 +12,9 @@ Contact: Anshuman Khandual <anshuman.khandual@arm.com>
|
|||
Description: (Read) Shows if TRBE updates in the memory are with access
|
||||
and dirty flag updates as well. This value is fetched from
|
||||
the TRBIDR register.
|
||||
|
||||
What: /sys/bus/coresight/devices/trbe<cpu>/label
|
||||
Date: Aug 2025
|
||||
KernelVersion 6.18
|
||||
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
|
||||
Description: (Read) Show hardware context information of device.
|
||||
|
|
|
|||
|
|
@ -309,26 +309,26 @@ Description:
|
|||
|
||||
What: /sys/bus/counter/devices/counterX/cascade_counts_enable_component_id
|
||||
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/compare_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/capture_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/ceiling_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/floor_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/compare_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/count_mode_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/direction_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/enable_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/error_noise_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/floor_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/num_overflows_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/prescaler_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/preset_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/preset_enable_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/signalZ_action_component_id
|
||||
What: /sys/bus/counter/devices/counterX/countY/num_overflows_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/cable_fault_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/cable_fault_enable_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/filter_clock_prescaler_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/frequency_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/index_polarity_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/polarity_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_component_id
|
||||
What: /sys/bus/counter/devices/counterX/signalY/frequency_component_id
|
||||
KernelVersion: 5.16
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
What: /sys/bus/i2c/devices/<busnum>-<primary-addr>/unlock
|
||||
Date: 2025-07-04
|
||||
KernelVersion: 6.17
|
||||
Contact: Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
Description:
|
||||
Write-only attribute used to present a password and unlock
|
||||
access to protected areas of the M24LR chip, including
|
||||
configuration registers such as the Sector Security Status
|
||||
(SSS) bytes. A valid password must be written to enable write
|
||||
access to these regions via the I2C interface.
|
||||
|
||||
Format:
|
||||
- Hexadecimal string representing a 32-bit (4-byte) password
|
||||
- Accepts 1 to 8 hex digits (e.g., "c", "1F", "a1b2c3d4")
|
||||
- No "0x" prefix, whitespace, or trailing newline
|
||||
- Case-insensitive
|
||||
|
||||
Behavior:
|
||||
- If the password matches the internal stored value,
|
||||
access to protected memory/configuration is granted
|
||||
- If the password does not match the internally stored value,
|
||||
it will fail silently
|
||||
|
||||
What: /sys/bus/i2c/devices/<busnum>-<primary-addr>/new_pass
|
||||
Date: 2025-07-04
|
||||
KernelVersion: 6.17
|
||||
Contact: Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
Description:
|
||||
Write-only attribute used to update the password required to
|
||||
unlock the M24LR chip.
|
||||
|
||||
Format:
|
||||
- Hexadecimal string representing a new 32-bit password
|
||||
- Accepts 1 to 8 hex digits (e.g., "1A", "ffff", "c0ffee00")
|
||||
- No "0x" prefix, whitespace, or trailing newline
|
||||
- Case-insensitive
|
||||
|
||||
Behavior:
|
||||
- Overwrites the current password stored in the I2C password
|
||||
register
|
||||
- Requires the device to be unlocked before changing the
|
||||
password
|
||||
- If the device is locked, the write silently fails
|
||||
|
||||
What: /sys/bus/i2c/devices/<busnum>-<primary-addr>/uid
|
||||
Date: 2025-07-04
|
||||
KernelVersion: 6.17
|
||||
Contact: Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
Description:
|
||||
Read-only attribute that exposes the 8-byte unique identifier
|
||||
programmed into the M24LR chip at the factory.
|
||||
|
||||
Format:
|
||||
- Lowercase hexadecimal string representing a 64-bit value
|
||||
- 1 to 16 hex digits (e.g., "e00204f12345678")
|
||||
- No "0x" prefix
|
||||
- Includes a trailing newline
|
||||
|
||||
What: /sys/bus/i2c/devices/<busnum>-<primary-addr>/total_sectors
|
||||
Date: 2025-07-04
|
||||
KernelVersion: 6.17
|
||||
Contact: Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
Description:
|
||||
Read-only attribute that exposes the total number of EEPROM
|
||||
sectors available in the M24LR chip.
|
||||
|
||||
Format:
|
||||
- 1 to 2 hex digits (e.g. "F")
|
||||
- No "0x" prefix
|
||||
- Includes a trailing newline
|
||||
|
||||
Notes:
|
||||
- Value is encoded by the chip and corresponds to the EEPROM
|
||||
size (e.g., 3 = 4 kbit for M24LR04E-R)
|
||||
|
||||
What: /sys/bus/i2c/devices/<busnum>-<primary-addr>/sss
|
||||
Date: 2025-07-04
|
||||
KernelVersion: 6.17
|
||||
Contact: Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
Description:
|
||||
Read/write binary attribute representing the Sector Security
|
||||
Status (SSS) bytes for all EEPROM sectors in STMicroelectronics
|
||||
M24LR chips.
|
||||
|
||||
Each EEPROM sector has one SSS byte, which controls I2C and
|
||||
RF access through protection bits and optional password
|
||||
authentication.
|
||||
|
||||
Format:
|
||||
- The file contains one byte per EEPROM sector
|
||||
- Byte at offset N corresponds to sector N
|
||||
- Binary access only; use tools like dd, Python, or C that
|
||||
support byte-level I/O and offset control.
|
||||
|
||||
Notes:
|
||||
- The number of valid bytes in this file is equal to the
|
||||
value exposed by 'total_sectors' file
|
||||
- Write access requires prior password authentication in
|
||||
I2C mode
|
||||
- Refer to the M24LR datasheet for full SSS bit layout
|
||||
|
|
@ -167,7 +167,18 @@ Description:
|
|||
is required is a consistent labeling. Units after application
|
||||
of scale and offset are millivolts.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltageY_rms_raw
|
||||
KernelVersion: 6.18
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
Raw (unscaled) Root Mean Square (RMS) voltage measurement from
|
||||
channel Y. Units after application of scale and offset are
|
||||
millivolts.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_powerY_raw
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_powerY_active_raw
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_powerY_reactive_raw
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_powerY_apparent_raw
|
||||
KernelVersion: 4.5
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
|
|
@ -176,6 +187,13 @@ Description:
|
|||
unique to allow association with event codes. Units after
|
||||
application of scale and offset are milliwatts.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_powerY_powerfactor
|
||||
KernelVersion: 6.18
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
Power factor measurement from channel Y. Power factor is the
|
||||
ratio of active power to apparent power. The value is unitless.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_capacitanceY_raw
|
||||
KernelVersion: 3.2
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
|
|
@ -1569,6 +1587,9 @@ Description:
|
|||
|
||||
What: /sys/.../iio:deviceX/in_energy_input
|
||||
What: /sys/.../iio:deviceX/in_energy_raw
|
||||
What: /sys/.../iio:deviceX/in_energyY_active_raw
|
||||
What: /sys/.../iio:deviceX/in_energyY_reactive_raw
|
||||
What: /sys/.../iio:deviceX/in_energyY_apparent_raw
|
||||
KernelVersion: 4.0
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
|
|
@ -1707,6 +1728,14 @@ Description:
|
|||
component of the signal while the 'q' channel contains the quadrature
|
||||
component.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_altcurrentY_rms_raw
|
||||
KernelVersion: 6.18
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
Raw (unscaled no bias removal etc.) Root Mean Square (RMS) current
|
||||
measurement from channel Y. Units after application of scale and
|
||||
offset are milliamps.
|
||||
|
||||
What: /sys/.../iio:deviceX/in_energy_en
|
||||
What: /sys/.../iio:deviceX/in_distance_en
|
||||
What: /sys/.../iio:deviceX/in_velocity_sqrt(x^2+y^2+z^2)_en
|
||||
|
|
@ -2281,21 +2310,28 @@ Description:
|
|||
conversion time. Poor noise performance.
|
||||
* "sinc3" - The digital sinc3 filter. Moderate 1st
|
||||
conversion time. Good noise performance.
|
||||
* "sinc4" - Sinc 4. Excellent noise performance. Long
|
||||
1st conversion time.
|
||||
* "sinc5" - The digital sinc5 filter. Excellent noise
|
||||
performance
|
||||
* "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion
|
||||
time.
|
||||
* "sinc3+rej60" - Sinc3 + 60Hz rejection.
|
||||
* "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion
|
||||
time.
|
||||
* "sinc3+pf1" - Sinc3 + device specific Post Filter 1.
|
||||
* "sinc3+pf2" - Sinc3 + device specific Post Filter 2.
|
||||
* "sinc3+pf3" - Sinc3 + device specific Post Filter 3.
|
||||
* "sinc3+pf4" - Sinc3 + device specific Post Filter 4.
|
||||
* "sinc5+pf1" - Sinc5 + device specific Post Filter 1.
|
||||
* "sinc3+rej60" - Sinc3 + 60Hz rejection.
|
||||
* "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion
|
||||
time.
|
||||
* "sinc4" - Sinc 4. Excellent noise performance. Long
|
||||
1st conversion time.
|
||||
* "sinc4+lp" - Sinc4 + Low Pass Filter.
|
||||
* "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion
|
||||
time.
|
||||
* "sinc4+rej60" - Sinc4 + 60Hz rejection.
|
||||
* "sinc5" - The digital sinc5 filter. Excellent noise
|
||||
performance
|
||||
* "sinc5+avg" - Sinc5 + averaging by 4.
|
||||
* "sinc5+pf1" - Sinc5 + device specific Post Filter 1.
|
||||
* "sinc5+sinc1" - Sinc5 + Sinc1.
|
||||
* "sinc5+sinc1+pf1" - Sinc5 + Sinc1 + device specific Post Filter 1.
|
||||
* "sinc5+sinc1+pf2" - Sinc5 + Sinc1 + device specific Post Filter 2.
|
||||
* "sinc5+sinc1+pf3" - Sinc5 + Sinc1 + device specific Post Filter 3.
|
||||
* "sinc5+sinc1+pf4" - Sinc5 + Sinc1 + device specific Post Filter 4.
|
||||
* "wideband" - filter with wideband low ripple passband
|
||||
and sharp transition band.
|
||||
|
||||
|
|
|
|||
|
|
@ -7,16 +7,6 @@ Description:
|
|||
corresponding calibration offsets can be read from `*_calibbias`
|
||||
entries.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/location
|
||||
Date: July 2015
|
||||
KernelVersion: 4.7
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
Description:
|
||||
This attribute returns a string with the physical location where
|
||||
the motion sensor is placed. For example, in a laptop a motion
|
||||
sensor can be located on the base or on the lid. Current valid
|
||||
values are 'base' and 'lid'.
|
||||
|
||||
What: /sys/bus/iio/devices/iio:deviceX/id
|
||||
Date: September 2017
|
||||
KernelVersion: 4.14
|
||||
|
|
|
|||
|
|
@ -612,3 +612,12 @@ Description:
|
|||
|
||||
# ls doe_features
|
||||
0001:01 0001:02 doe_discovery
|
||||
|
||||
What: /sys/bus/pci/devices/.../serial_number
|
||||
Date: December 2025
|
||||
Contact: Matthew Wood <thepacketgeek@gmail.com>
|
||||
Description:
|
||||
This is visible only for PCI devices that support the serial
|
||||
number extended capability. The file is read only and due to
|
||||
the possible sensitivity of accessible serial numbers, admin
|
||||
only.
|
||||
|
|
|
|||
|
|
@ -90,8 +90,9 @@ of the function device and is populated with the following NTB specific
|
|||
attributes that can be configured by the user::
|
||||
|
||||
# ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/
|
||||
db_count mw1 mw2 mw3 mw4 num_mws
|
||||
spad_count
|
||||
ctrl_bar db_count mw1_bar mw2_bar mw3_bar mw4_bar spad_count
|
||||
db_bar mw1 mw2 mw3 mw4 num_mws vbus_number
|
||||
vntb_vid vntb_pid
|
||||
|
||||
A sample configuration for NTB function is given below::
|
||||
|
||||
|
|
@ -100,6 +101,10 @@ A sample configuration for NTB function is given below::
|
|||
# echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws
|
||||
# echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1
|
||||
|
||||
By default, each construct is assigned a BAR, as needed and in order.
|
||||
Should a specific BAR setup be required by the platform, BAR may be assigned
|
||||
to each construct using the related ``XYZ_bar`` entry.
|
||||
|
||||
A sample configuration for virtual NTB driver for virtual PCI bus::
|
||||
|
||||
# echo 0x1957 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/vntb_vid
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ PCI Error Recovery
|
|||
Many PCI bus controllers are able to detect a variety of hardware
|
||||
PCI errors on the bus, such as parity errors on the data and address
|
||||
buses, as well as SERR and PERR errors. Some of the more advanced
|
||||
chipsets are able to deal with these errors; these include PCI-E chipsets,
|
||||
chipsets are able to deal with these errors; these include PCIe chipsets,
|
||||
and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
|
||||
pSeries boxes. A typical action taken is to disconnect the affected device,
|
||||
halting all I/O to it. The goal of a disconnection is to avoid system
|
||||
|
|
@ -108,8 +108,8 @@ A driver does not have to implement all of these callbacks; however,
|
|||
if it implements any, it must implement error_detected(). If a callback
|
||||
is not implemented, the corresponding feature is considered unsupported.
|
||||
For example, if mmio_enabled() and resume() aren't there, then it
|
||||
is assumed that the driver is not doing any direct recovery and requires
|
||||
a slot reset. Typically a driver will want to know about
|
||||
is assumed that the driver does not need these callbacks
|
||||
for recovery. Typically a driver will want to know about
|
||||
a slot_reset().
|
||||
|
||||
The actual steps taken by a platform to recover from a PCI error
|
||||
|
|
@ -122,6 +122,10 @@ A PCI bus error is detected by the PCI hardware. On powerpc, the slot
|
|||
is isolated, in that all I/O is blocked: all reads return 0xffffffff,
|
||||
all writes are ignored.
|
||||
|
||||
Similarly, on platforms supporting Downstream Port Containment
|
||||
(PCIe r7.0 sec 6.2.11), the link to the sub-hierarchy with the
|
||||
faulting device is disabled. Any device in the sub-hierarchy
|
||||
becomes inaccessible.
|
||||
|
||||
STEP 1: Notification
|
||||
--------------------
|
||||
|
|
@ -141,6 +145,9 @@ shouldn't do any new IOs. Called in task context. This is sort of a
|
|||
All drivers participating in this system must implement this call.
|
||||
The driver must return one of the following result codes:
|
||||
|
||||
- PCI_ERS_RESULT_RECOVERED
|
||||
Driver returns this if it thinks the device is usable despite
|
||||
the error and does not need further intervention.
|
||||
- PCI_ERS_RESULT_CAN_RECOVER
|
||||
Driver returns this if it thinks it might be able to recover
|
||||
the HW by just banging IOs or if it wants to be given
|
||||
|
|
@ -199,7 +206,25 @@ reset or some such, but not restart operations. This callback is made if
|
|||
all drivers on a segment agree that they can try to recover and if no automatic
|
||||
link reset was performed by the HW. If the platform can't just re-enable IOs
|
||||
without a slot reset or a link reset, it will not call this callback, and
|
||||
instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
|
||||
instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset).
|
||||
|
||||
.. note::
|
||||
|
||||
On platforms supporting Advanced Error Reporting (PCIe r7.0 sec 6.2),
|
||||
the faulting device may already be accessible in STEP 1 (Notification).
|
||||
Drivers should nevertheless defer accesses to STEP 2 (MMIO Enabled)
|
||||
to be compatible with EEH on powerpc and with s390 (where devices are
|
||||
inaccessible until STEP 2).
|
||||
|
||||
On platforms supporting Downstream Port Containment, the link to the
|
||||
sub-hierarchy with the faulting device is re-enabled in STEP 3 (Link
|
||||
Reset). Hence devices in the sub-hierarchy are inaccessible until
|
||||
STEP 4 (Slot Reset).
|
||||
|
||||
For errors such as Surprise Down (PCIe r7.0 sec 6.2.7), the device
|
||||
may not even be accessible in STEP 4 (Slot Reset). Drivers can detect
|
||||
accessibility by checking whether reads from the device return all 1's
|
||||
(PCI_POSSIBLE_ERROR()).
|
||||
|
||||
.. note::
|
||||
|
||||
|
|
@ -234,14 +259,14 @@ The driver should return one of the following result codes:
|
|||
|
||||
The next step taken depends on the results returned by the drivers.
|
||||
If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform
|
||||
proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
|
||||
proceeds to either STEP 3 (Link Reset) or to STEP 5 (Resume Operations).
|
||||
|
||||
If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
|
||||
proceeds to STEP 4 (Slot Reset)
|
||||
|
||||
STEP 3: Link Reset
|
||||
------------------
|
||||
The platform resets the link. This is a PCI-Express specific step
|
||||
The platform resets the link. This is a PCIe specific step
|
||||
and is done whenever a fatal error has been detected that can be
|
||||
"solved" by resetting the link.
|
||||
|
||||
|
|
@ -263,13 +288,13 @@ that is equivalent to what it would be after a fresh system
|
|||
power-on followed by power-on BIOS/system firmware initialization.
|
||||
Soft reset is also known as hot-reset.
|
||||
|
||||
Powerpc fundamental reset is supported by PCI Express cards only
|
||||
Powerpc fundamental reset is supported by PCIe cards only
|
||||
and results in device's state machines, hardware logic, port states and
|
||||
configuration registers to initialize to their default conditions.
|
||||
|
||||
For most PCI devices, a soft reset will be sufficient for recovery.
|
||||
Optional fundamental reset is provided to support a limited number
|
||||
of PCI Express devices for which a soft reset is not sufficient
|
||||
of PCIe devices for which a soft reset is not sufficient
|
||||
for recovery.
|
||||
|
||||
If the platform supports PCI hotplug, then the reset might be
|
||||
|
|
@ -313,7 +338,7 @@ Result codes:
|
|||
- PCI_ERS_RESULT_DISCONNECT
|
||||
Same as above.
|
||||
|
||||
Drivers for PCI Express cards that require a fundamental reset must
|
||||
Drivers for PCIe cards that require a fundamental reset must
|
||||
set the needs_freset bit in the pci_dev structure in their probe function.
|
||||
For example, the QLogic qla2xxx driver sets the needs_freset bit for certain
|
||||
PCI card types::
|
||||
|
|
|
|||
|
|
@ -70,16 +70,16 @@ AER error output
|
|||
----------------
|
||||
|
||||
When a PCIe AER error is captured, an error message will be output to
|
||||
console. If it's a correctable error, it is output as an info message.
|
||||
console. If it's a correctable error, it is output as a warning message.
|
||||
Otherwise, it is printed as an error. So users could choose different
|
||||
log level to filter out correctable error messages.
|
||||
|
||||
Below shows an example::
|
||||
|
||||
0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)
|
||||
0000:50:00.0: PCIe Bus Error: severity=Uncorrectable (Fatal), type=Transaction Layer, (Requester ID)
|
||||
0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
|
||||
0000:50:00.0: [20] Unsupported Request (First)
|
||||
0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
|
||||
0000:50:00.0: [20] UnsupReq (First)
|
||||
0000:50:00.0: TLP Header: 0x04000001 0x00200a03 0x05010000 0x00050100
|
||||
|
||||
In the example, 'Requester ID' means the ID of the device that sent
|
||||
the error message to the Root Port. Please refer to PCIe specs for other
|
||||
|
|
@ -138,7 +138,7 @@ error message to the Root Port above it when it captures
|
|||
an error. The Root Port, upon receiving an error reporting message,
|
||||
internally processes and logs the error message in its AER
|
||||
Capability structure. Error information being logged includes storing
|
||||
the error reporting agent's requestor ID into the Error Source
|
||||
the error reporting agent's Requester ID into the Error Source
|
||||
Identification Registers and setting the error bits of the Root Error
|
||||
Status Register accordingly. If AER error reporting is enabled in the Root
|
||||
Error Command Register, the Root Port generates an interrupt when an
|
||||
|
|
@ -152,18 +152,6 @@ the device driver.
|
|||
Provide callbacks
|
||||
-----------------
|
||||
|
||||
callback reset_link to reset PCIe link
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This callback is used to reset the PCIe physical link when a
|
||||
fatal error happens. The Root Port AER service driver provides a
|
||||
default reset_link function, but different Upstream Ports might
|
||||
have different specifications to reset the PCIe link, so
|
||||
Upstream Port drivers may provide their own reset_link functions.
|
||||
|
||||
Section 3.2.2.2 provides more detailed info on when to call
|
||||
reset_link.
|
||||
|
||||
PCI error-recovery callbacks
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
|
@ -174,8 +162,8 @@ when performing error recovery actions.
|
|||
Data struct pci_driver has a pointer, err_handler, to point to
|
||||
pci_error_handlers who consists of a couple of callback function
|
||||
pointers. The AER driver follows the rules defined in
|
||||
pci-error-recovery.rst except PCIe-specific parts (e.g.
|
||||
reset_link). Please refer to pci-error-recovery.rst for detailed
|
||||
pci-error-recovery.rst except PCIe-specific parts (see
|
||||
below). Please refer to pci-error-recovery.rst for detailed
|
||||
definitions of the callbacks.
|
||||
|
||||
The sections below specify when to call the error callback functions.
|
||||
|
|
@ -189,10 +177,21 @@ software intervention or any loss of data. These errors do not
|
|||
require any recovery actions. The AER driver clears the device's
|
||||
correctable error status register accordingly and logs these errors.
|
||||
|
||||
Non-correctable (non-fatal and fatal) errors
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
Uncorrectable (non-fatal and fatal) errors
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If an error message indicates a non-fatal error, performing link reset
|
||||
The AER driver performs a Secondary Bus Reset to recover from
|
||||
uncorrectable errors. The reset is applied at the port above
|
||||
the originating device: If the originating device is an Endpoint,
|
||||
only the Endpoint is reset. If on the other hand the originating
|
||||
device has subordinate devices, those are all affected by the
|
||||
reset as well.
|
||||
|
||||
If the originating device is a Root Complex Integrated Endpoint,
|
||||
there's no port above where a Secondary Bus Reset could be applied.
|
||||
In this case, the AER driver instead applies a Function Level Reset.
|
||||
|
||||
If an error message indicates a non-fatal error, performing a reset
|
||||
at upstream is not required. The AER driver calls error_detected(dev,
|
||||
pci_channel_io_normal) to all drivers associated within a hierarchy in
|
||||
question. For example::
|
||||
|
|
@ -204,38 +203,34 @@ Downstream Port B and Endpoint.
|
|||
|
||||
A driver may return PCI_ERS_RESULT_CAN_RECOVER,
|
||||
PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
|
||||
whether it can recover or the AER driver calls mmio_enabled as next.
|
||||
whether it can recover without a reset, considers the device unrecoverable
|
||||
or needs a reset for recovery. If all affected drivers agree that they can
|
||||
recover without a reset, it is skipped. Should one driver request a reset,
|
||||
it overrides all other drivers.
|
||||
|
||||
If an error message indicates a fatal error, kernel will broadcast
|
||||
error_detected(dev, pci_channel_io_frozen) to all drivers within
|
||||
a hierarchy in question. Then, performing link reset at upstream is
|
||||
necessary. As different kinds of devices might use different approaches
|
||||
to reset link, AER port service driver is required to provide the
|
||||
function to reset link via callback parameter of pcie_do_recovery()
|
||||
function. If reset_link is not NULL, recovery function will use it
|
||||
to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER
|
||||
and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
|
||||
to mmio_enabled.
|
||||
a hierarchy in question. Then, performing a reset at upstream is
|
||||
necessary. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER
|
||||
to indicate that recovery without a reset is possible, the error
|
||||
handling goes to mmio_enabled, but afterwards a reset is still
|
||||
performed.
|
||||
|
||||
Frequent Asked Questions
|
||||
------------------------
|
||||
In other words, for non-fatal errors, drivers may opt in to a reset.
|
||||
But for fatal errors, they cannot opt out of a reset, based on the
|
||||
assumption that the link is unreliable.
|
||||
|
||||
Frequently Asked Questions
|
||||
--------------------------
|
||||
|
||||
Q:
|
||||
What happens if a PCIe device driver does not provide an
|
||||
error recovery handler (pci_driver->err_handler is equal to NULL)?
|
||||
|
||||
A:
|
||||
The devices attached with the driver won't be recovered. If the
|
||||
error is fatal, kernel will print out warning messages. Please refer
|
||||
to section 3 for more information.
|
||||
|
||||
Q:
|
||||
What happens if an upstream port service driver does not provide
|
||||
callback reset_link?
|
||||
|
||||
A:
|
||||
Fatal error recovery will fail if the errors are reported by the
|
||||
upstream ports who are attached by the service driver.
|
||||
The devices attached with the driver won't be recovered.
|
||||
The kernel will print out informational messages to identify
|
||||
unrecoverable devices.
|
||||
|
||||
|
||||
Software error injection
|
||||
|
|
|
|||
|
|
@ -608,6 +608,24 @@
|
|||
ccw_timeout_log [S390]
|
||||
See Documentation/arch/s390/common_io.rst for details.
|
||||
|
||||
cfi= [X86-64] Set Control Flow Integrity checking features
|
||||
when CONFIG_FINEIBT is enabled.
|
||||
Format: feature[,feature...]
|
||||
Default: auto
|
||||
|
||||
auto: Use FineIBT if IBT available, otherwise kCFI.
|
||||
Under FineIBT, enable "paranoid" mode when
|
||||
FRED is not available.
|
||||
off: Turn off CFI checking.
|
||||
kcfi: Use kCFI (disable FineIBT).
|
||||
fineibt: Use FineIBT (even if IBT not available).
|
||||
norand: Do not re-randomize CFI hashes.
|
||||
paranoid: Add caller hash checking under FineIBT.
|
||||
bhi: Enable register poisoning to stop speculation
|
||||
across FineIBT. (Disabled by default.)
|
||||
warn: Do not enforce CFI checking: warn only.
|
||||
debug: Report CFI initialization details.
|
||||
|
||||
cgroup_disable= [KNL] Disable a particular controller or optional feature
|
||||
Format: {name of the controller(s) or feature(s) to disable}
|
||||
The effects of cgroup_disable=foo are:
|
||||
|
|
@ -2962,6 +2980,27 @@
|
|||
(enabled). Disable by KVM if hardware lacks support
|
||||
for NPT.
|
||||
|
||||
kvm-amd.ciphertext_hiding_asids=
|
||||
[KVM,AMD] Ciphertext hiding prevents disallowed accesses
|
||||
to SNP private memory from reading ciphertext. Instead,
|
||||
reads will see constant default values (0xff).
|
||||
|
||||
If ciphertext hiding is enabled, the joint SEV-ES and
|
||||
SEV-SNP ASID space is partitioned into separate SEV-ES
|
||||
and SEV-SNP ASID ranges, with the SEV-SNP range being
|
||||
[1..max_snp_asid] and the SEV-ES range being
|
||||
(max_snp_asid..min_sev_asid), where min_sev_asid is
|
||||
enumerated by CPUID.0x.8000_001F[EDX].
|
||||
|
||||
A non-zero value enables SEV-SNP ciphertext hiding and
|
||||
adjusts the ASID ranges for SEV-ES and SEV-SNP guests.
|
||||
KVM caps the number of SEV-SNP ASIDs at the maximum
|
||||
possible value, e.g. specifying -1u will assign all
|
||||
joint SEV-ES and SEV-SNP ASIDs to SEV-SNP. Note,
|
||||
assigning all joint ASIDs to SEV-SNP, i.e. configuring
|
||||
max_snp_asid == min_sev_asid-1, will effectively make
|
||||
SEV-ES unusable.
|
||||
|
||||
kvm-arm.mode=
|
||||
[KVM,ARM,EARLY] Select one of KVM/arm64's modes of
|
||||
operation.
|
||||
|
|
|
|||
|
|
@ -15,15 +15,19 @@ The driver provides a description of its available events and configuration
|
|||
options in sysfs, see /sys/bus/event_sources/devices/mac_iod<iod>_mac<mac>_ch<ch>/
|
||||
and /sys/bus/event_sources/devices/pci_iod<iod>_pci<pci>/.
|
||||
This driver exports:
|
||||
|
||||
- formats, used by perf user space and other tools to configure events
|
||||
- events, used by perf user space and other tools to create events
|
||||
symbolically, e.g.:
|
||||
symbolically, e.g.::
|
||||
|
||||
perf stat -a -e mac_iod0_mac0_ch0/event=0x21/ ls
|
||||
perf stat -a -e pci_iod0_pci0/event=0x24/ ls
|
||||
|
||||
- cpumask, used by perf user space and other tools to know on which CPUs
|
||||
to open the events
|
||||
|
||||
This driver supports the following events for MAC:
|
||||
|
||||
- cycles
|
||||
This event counts MAC cycles at MAC frequency.
|
||||
- read-count
|
||||
|
|
@ -77,6 +81,7 @@ Examples for use with perf::
|
|||
perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls
|
||||
|
||||
And, this driver supports the following events for PCI:
|
||||
|
||||
- pci-port0-cycles
|
||||
This event counts PCI cycles at PCI frequency in port0.
|
||||
- pci-port0-read-count
|
||||
|
|
|
|||
|
|
@ -66,6 +66,10 @@ specified as a bitmap::
|
|||
|
||||
This will only count the operations from core/thread 0 and 1 in this cluster.
|
||||
|
||||
User should not use tt_core_deprecated to specify the core/thread filtering.
|
||||
This option is provided for backward compatiblility and only support 8bit
|
||||
which may not cover all the core/thread sharing L3C.
|
||||
|
||||
2. Tracetag allow the user to chose to count only read, write or atomic
|
||||
operations via the tt_req parameeter in perf. The default value counts all
|
||||
operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101
|
||||
|
|
|
|||
|
|
@ -274,10 +274,6 @@ are the following:
|
|||
The time it takes to switch the CPUs belonging to this policy from one
|
||||
P-state to another, in nanoseconds.
|
||||
|
||||
If unknown or if known to be so high that the scaling driver does not
|
||||
work with the `ondemand`_ governor, -1 (:c:macro:`CPUFREQ_ETERNAL`)
|
||||
will be returned by reads from this attribute.
|
||||
|
||||
``related_cpus``
|
||||
List of all (online and offline) CPUs belonging to this policy.
|
||||
|
||||
|
|
|
|||
|
|
@ -109,8 +109,7 @@ Then, the driver must fill in the following values:
|
|||
+-----------------------------------+--------------------------------------+
|
||||
|policy->cpuinfo.transition_latency | the time it takes on this CPU to |
|
||||
| | switch between two frequencies in |
|
||||
| | nanoseconds (if appropriate, else |
|
||||
| | specify CPUFREQ_ETERNAL) |
|
||||
| | nanoseconds |
|
||||
+-----------------------------------+--------------------------------------+
|
||||
|policy->cur | The current operating frequency of |
|
||||
| | this CPU (if appropriate) |
|
||||
|
|
|
|||
|
|
@ -98,6 +98,10 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
arm,cti-ctm-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ properties:
|
|||
enum:
|
||||
- arm,coresight-dummy-sink
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,10 @@ properties:
|
|||
enum:
|
||||
- arm,coresight-dummy-source
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
arm,static-trace-id:
|
||||
description: If dummy source needs static id support, use this to set trace id.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
|
|
|||
|
|
@ -57,6 +57,10 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,10 @@ properties:
|
|||
- const: apb_pclk
|
||||
- const: atclk
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,10 @@ properties:
|
|||
- const: apb_pclk
|
||||
- const: atclk
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -85,6 +85,10 @@ properties:
|
|||
CPU powers down the coresight component also powers down and loses its
|
||||
context.
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
arm,cp14:
|
||||
type: boolean
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -30,6 +30,10 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ properties:
|
|||
- const: dbg_trc
|
||||
- const: dbg_apb
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
|
|
|||
|
|
@ -55,6 +55,10 @@ properties:
|
|||
- const: apb_pclk
|
||||
- const: atclk
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,10 @@ properties:
|
|||
- const: apb_pclk
|
||||
- const: atclk
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -103,6 +103,28 @@ properties:
|
|||
- compatible
|
||||
- "#pwm-cells"
|
||||
|
||||
touchscreen:
|
||||
type: object
|
||||
$ref: /schemas/input/touchscreen/touchscreen.yaml#
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: raspberrypi,firmware-ts
|
||||
|
||||
firmware:
|
||||
deprecated: true
|
||||
description: Phandle to RPi's firmware device node.
|
||||
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
|
|
@ -135,5 +157,11 @@ examples:
|
|||
compatible = "raspberrypi,firmware-poe-pwm";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
ts: touchscreen {
|
||||
compatible = "raspberrypi,firmware-ts";
|
||||
touchscreen-size-x = <800>;
|
||||
touchscreen-size-y = <480>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ properties:
|
|||
items:
|
||||
- const: apb
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@ properties:
|
|||
compatible:
|
||||
const: qcom,coresight-remote-etm
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
out-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
|
|
|||
|
|
@ -0,0 +1,113 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Trace Network On Chip - TNOC
|
||||
|
||||
maintainers:
|
||||
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
|
||||
|
||||
description: >
|
||||
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
|
||||
component that integrates the functionalities of TPDA and funnels.
|
||||
|
||||
It sits in the different subsystem of SOC and aggregates the trace and
|
||||
transports it to Aggregation TNOC or to coresight trace sink eventually.
|
||||
TNOC embeds bridges for all the interfaces APB, ATB, TPDA and NTS (Narrow
|
||||
Time Stamp).
|
||||
|
||||
TNOC can take inputs from different trace sources i.e. ATB, TPDM.
|
||||
|
||||
Note this binding is specifically intended for Aggregator TNOC instances.
|
||||
|
||||
# Need a custom select here or 'arm,primecell' will match on lots of nodes
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,coresight-tnoc
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^tn(@[0-9a-f]+)$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,coresight-tnoc
|
||||
- const: arm,primecell
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb_pclk
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: APB register access clock
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
patternProperties:
|
||||
'^port(@[0-9a-f]{1,2})?$':
|
||||
description: Input connections from CoreSight Trace Bus
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
out-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
port:
|
||||
description:
|
||||
Output connection to CoreSight Trace Bus
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- in-ports
|
||||
- out-ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
tn@109ab000 {
|
||||
compatible = "qcom,coresight-tnoc", "arm,primecell";
|
||||
reg = <0x109ab000 0x4200>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tn_ag_in_tpdm_gcc: endpoint {
|
||||
remote-endpoint = <&tpdm_gcc_out_tn_ag>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
tn_ag_out_funnel_in1: endpoint {
|
||||
remote-endpoint = <&funnel_in1_in_tn_ag>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -64,6 +64,10 @@ properties:
|
|||
items:
|
||||
- const: apb_pclk
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
in-ports:
|
||||
description: |
|
||||
Input connections from TPDM to TPDA
|
||||
|
|
|
|||
|
|
@ -76,6 +76,10 @@ properties:
|
|||
minimum: 0
|
||||
maximum: 32
|
||||
|
||||
label:
|
||||
description:
|
||||
Description of a coresight device.
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -9,14 +9,11 @@ title: APM X-Gene 6.0 Gb/s SATA host controller
|
|||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- apm,xgene-ahci
|
||||
- apm,xgene-ahci-pcie
|
||||
- apm,xgene-ahci-v2
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
|
|
@ -35,12 +32,22 @@ properties:
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: apm,xgene-ahci
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@1a400000 {
|
||||
|
|
|
|||
|
|
@ -80,6 +80,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
target-supply:
|
||||
description: Power regulator for the SATA target device.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ examples:
|
|||
dma-coherent;
|
||||
calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
|
||||
<&combophy0 2>, <&combophy0 3>;
|
||||
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
|
||||
calxeda,sgpio-gpio = <&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
|
||||
calxeda,led-order = <4 0 1 2 3>;
|
||||
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
|
||||
calxeda,pre-clocks = <10>;
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ properties:
|
|||
|
||||
patternProperties:
|
||||
# All other properties should be child nodes with unit-address and 'reg'
|
||||
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
|
||||
"@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -41,6 +41,18 @@ properties:
|
|||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
# All other properties should be child nodes with unit-address and 'reg'
|
||||
"@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ properties:
|
|||
- const: clkin2
|
||||
- const: s_axi_aclk
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
|
|
@ -65,4 +68,5 @@ examples:
|
|||
reg = <0xff000000 0x1000>;
|
||||
clocks = <&osc 1>, <&clkc 15>;
|
||||
clock-names = "clkin1", "s_axi_aclk";
|
||||
clock-output-names = "spi_sclk";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,26 +0,0 @@
|
|||
Fujitsu CRG11 clock driver bindings
|
||||
-----------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : Shall contain "fujitsu,mb86s70-crg11"
|
||||
- #clock-cells : Shall be 3 {cntrlr domain port}
|
||||
|
||||
The consumer specifies the desired clock pointing to its phandle.
|
||||
|
||||
Example:
|
||||
|
||||
clock: crg11 {
|
||||
compatible = "fujitsu,mb86s70-crg11";
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
|
||||
mhu: mhu0@2b1f0000 {
|
||||
#mbox-cells = <1>;
|
||||
compatible = "arm,mhu";
|
||||
reg = <0 0x2B1F0000 0x1000>;
|
||||
interrupts = <0 36 4>, /* LP Non-Sec */
|
||||
<0 35 4>, /* HP Non-Sec */
|
||||
<0 37 4>; /* Secure */
|
||||
clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
|
||||
clock-names = "clk";
|
||||
};
|
||||
|
|
@ -16,6 +16,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- loongson,ls2k0300-clk
|
||||
- loongson,ls2k0500-clk
|
||||
- loongson,ls2k-clk # This is for Loongson-2K1000
|
||||
- loongson,ls2k2000-clk
|
||||
|
|
@ -24,8 +25,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 100m ref
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
|
@ -38,11 +38,23 @@ properties:
|
|||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
|
||||
for the full list of Loongson-2 SoC clock IDs.
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: loongson,ls2k0300-clk
|
||||
then:
|
||||
properties:
|
||||
clock-names: false
|
||||
else:
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
|
|
|||
|
|
@ -0,0 +1,112 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8196
|
||||
|
||||
maintainers:
|
||||
- Guangjie Song <guangjie.song@mediatek.com>
|
||||
- Laura Nao <laura.nao@collabora.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek SoCs is structured like below:
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The device nodes provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8196-imp-iic-wrap-c
|
||||
- mediatek,mt8196-imp-iic-wrap-e
|
||||
- mediatek,mt8196-imp-iic-wrap-n
|
||||
- mediatek,mt8196-imp-iic-wrap-w
|
||||
- mediatek,mt8196-mdpsys0
|
||||
- mediatek,mt8196-mdpsys1
|
||||
- mediatek,mt8196-pericfg-ao
|
||||
- mediatek,mt8196-pextp0cfg-ao
|
||||
- mediatek,mt8196-pextp1cfg-ao
|
||||
- mediatek,mt8196-ufscfg-ao
|
||||
- mediatek,mt8196-vencsys
|
||||
- mediatek,mt8196-vencsys-c1
|
||||
- mediatek,mt8196-vencsys-c2
|
||||
- mediatek,mt8196-vdecsys
|
||||
- mediatek,mt8196-vdecsys-soc
|
||||
- mediatek,mt8196-vdisp-ao
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
description:
|
||||
Reset lines for PEXTP0/1 and UFS blocks.
|
||||
|
||||
mediatek,hardware-voter:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Phandle to the "Hardware Voter" (HWV), as named in the vendor
|
||||
documentation for MT8196/MT6991.
|
||||
|
||||
The HWV is a SoC-internal fixed-function MCU used to collect votes from
|
||||
both the Application Processor and other remote processors within the SoC.
|
||||
It is intended to transparently enable or disable hardware resources (such
|
||||
as power domains or clocks) based on internal vote aggregation handled by
|
||||
the MCU's internal state machine.
|
||||
|
||||
However, in practice, this design is incomplete. While the HWV performs
|
||||
some internal vote aggregation,software is still required to
|
||||
- Manually enable power supplies externally, if present and if required
|
||||
- Manually enable parent clocks via direct MMIO writes to clock controllers
|
||||
- Enable the FENC after the clock has been ungated via direct MMIO
|
||||
writes to clock controllers
|
||||
|
||||
As such, the HWV behaves more like a hardware-managed clock reference
|
||||
counter than a true voter. Furthermore, it is not a separate
|
||||
controller. It merely serves as an alternative interface to the same
|
||||
underlying clock or power controller. Actual control still requires
|
||||
direct access to the controller's own MMIO register space, in
|
||||
addition to writing to the HWV's MMIO region.
|
||||
|
||||
For this reason, a custom phandle is used here - drivers need to directly
|
||||
access the HWV MMIO region in a syscon-like fashion, due to how the
|
||||
hardware is wired. This differs from true hardware voting systems, which
|
||||
typically do not require custom phandles and rely instead on generic APIs
|
||||
(clocks, power domains, interconnects).
|
||||
|
||||
The name "hardware-voter" is retained to match vendor documentation, but
|
||||
this should not be reused or misunderstood as a proper voting mechanism.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pericfg_ao: clock-controller@16640000 {
|
||||
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
|
||||
reg = <0x16640000 0x1000>;
|
||||
mediatek,hardware-voter = <&scp_hwv>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
- |
|
||||
pextp0cfg_ao: clock-controller@169b0000 {
|
||||
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
|
||||
reg = <0x169b0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8196
|
||||
|
||||
maintainers:
|
||||
- Guangjie Song <guangjie.song@mediatek.com>
|
||||
- Laura Nao <laura.nao@collabora.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek SoCs is structured like below:
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
|
||||
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
|
||||
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
|
||||
provide the clock source to other IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8196-apmixedsys
|
||||
- mediatek,mt8196-armpll-b-pll-ctrl
|
||||
- mediatek,mt8196-armpll-bl-pll-ctrl
|
||||
- mediatek,mt8196-armpll-ll-pll-ctrl
|
||||
- mediatek,mt8196-apmixedsys-gp2
|
||||
- mediatek,mt8196-ccipll-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
|
||||
- mediatek,mt8196-ptppll-pll-ctrl
|
||||
- mediatek,mt8196-topckgen
|
||||
- mediatek,mt8196-topckgen-gp2
|
||||
- mediatek,mt8196-vlpckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
mediatek,hardware-voter:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Phandle to the "Hardware Voter" (HWV), as named in the vendor
|
||||
documentation for MT8196/MT6991.
|
||||
|
||||
The HWV is a SoC-internal fixed-function MCU used to collect votes from
|
||||
both the Application Processor and other remote processors within the SoC.
|
||||
It is intended to transparently enable or disable hardware resources (such
|
||||
as power domains or clocks) based on internal vote aggregation handled by
|
||||
the MCU's internal state machine.
|
||||
|
||||
However, in practice, this design is incomplete. While the HWV performs
|
||||
some internal vote aggregation,software is still required to
|
||||
- Manually enable power supplies externally, if present and if required
|
||||
- Manually enable parent clocks via direct MMIO writes to clock controllers
|
||||
- Enable the FENC after the clock has been ungated via direct MMIO
|
||||
writes to clock controllers
|
||||
|
||||
As such, the HWV behaves more like a hardware-managed clock reference
|
||||
counter than a true voter. Furthermore, it is not a separate
|
||||
controller. It merely serves as an alternative interface to the same
|
||||
underlying clock or power controller. Actual control still requires
|
||||
direct access to the controller's own MMIO register space, in
|
||||
addition to writing to the HWV's MMIO region.
|
||||
|
||||
For this reason, a custom phandle is used here - drivers need to directly
|
||||
access the HWV MMIO region in a syscon-like fashion, due to how the
|
||||
hardware is wired. This differs from true hardware voting systems, which
|
||||
typically do not require custom phandles and rely instead on generic APIs
|
||||
(clocks, power domains, interconnects).
|
||||
|
||||
The name "hardware-voter" is retained to match vendor documentation, but
|
||||
this should not be reused or misunderstood as a proper voting mechanism.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apmixedsys_clk: syscon@10000800 {
|
||||
compatible = "mediatek,mt8196-apmixedsys", "syscon";
|
||||
reg = <0x10000800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8196-topckgen", "syscon";
|
||||
reg = <0x10000000 0x800>;
|
||||
mediatek,hardware-voter = <&scp_hwv>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
@ -76,6 +76,9 @@ properties:
|
|||
- const: mediatek,mt2701-vdecsys
|
||||
- const: syscon
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
|
@ -86,6 +89,18 @@ required:
|
|||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-mfgcfg
|
||||
then:
|
||||
properties:
|
||||
power-domains: true
|
||||
else:
|
||||
properties:
|
||||
power-domains: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953
|
|||
maintainers:
|
||||
- Adam Skladowski <a_skl39@protonmail.com>
|
||||
- Sireesh Kodali <sireeshkodali@protonmail.com>
|
||||
- Barnabas Czeman <barnabas.czeman@mainlining.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8953.
|
||||
domains on MSM8937 or MSM8953.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8917.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8953
|
||||
enum:
|
||||
- qcom,gcc-msm8937
|
||||
- qcom,gcc-msm8953
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on GLYMUR
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains for the MDSS instances on GLYMUR SoC.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,dispcc-glymur.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board CXO clock
|
||||
- description: Board sleep clock
|
||||
- description: DisplayPort 0 link clock
|
||||
- description: DisplayPort 0 VCO div clock
|
||||
- description: DisplayPort 1 link clock
|
||||
- description: DisplayPort 1 VCO div clock
|
||||
- description: DisplayPort 2 link clock
|
||||
- description: DisplayPort 2 VCO div clock
|
||||
- description: DisplayPort 3 link clock
|
||||
- description: DisplayPort 3 VCO div clock
|
||||
- description: DSI 0 PLL byte clock
|
||||
- description: DSI 0 PLL DSI clock
|
||||
- description: DSI 1 PLL byte clock
|
||||
- description: DSI 1 PLL DSI clock
|
||||
- description: Standalone PHY 0 PLL link clock
|
||||
- description: Standalone PHY 0 VCO div clock
|
||||
- description: Standalone PHY 1 PLL link clock
|
||||
- description: Standalone PHY 1 VCO div clock
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,glymur-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&mdss_dp_phy0 0>,
|
||||
<&mdss_dp_phy0 1>,
|
||||
<&mdss_dp_phy1 0>,
|
||||
<&mdss_dp_phy1 1>,
|
||||
<&mdss_dp_phy2 0>,
|
||||
<&mdss_dp_phy2 1>,
|
||||
<&mdss_dp_phy3 0>,
|
||||
<&mdss_dp_phy3 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&mdss_phy0_link 0>,
|
||||
<&mdss_phy0_vco_div 0>,
|
||||
<&mdss_phy1_link 1>,
|
||||
<&mdss_phy1_vco_div 1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on Glymur SoC
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on Glymur SoC.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,glymur-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,glymur-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO_A source
|
||||
- description: Sleep clock source
|
||||
- description: USB 0 Phy DP0 GMUX clock source
|
||||
- description: USB 0 Phy DP1 GMUX clock source
|
||||
- description: USB 0 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 0 Phy PIPEGMUX clock source
|
||||
- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: USB 1 Phy DP0 GMUX 2 clock source
|
||||
- description: USB 1 Phy DP1 GMUX 2 clock source
|
||||
- description: USB 1 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 1 Phy PIPEGMUX clock source
|
||||
- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: USB 2 Phy DP0 GMUX 2 clock source
|
||||
- description: USB 2 Phy DP1 GMUX 2 clock source
|
||||
- description: USB 2 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 2 Phy PIPEGMUX clock source
|
||||
- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: PCIe 3a pipe clock
|
||||
- description: PCIe 3b pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: PCIe 5 pipe clock
|
||||
- description: PCIe 6 pipe clock
|
||||
- description: QUSB4 0 PHY RX 0 clock source
|
||||
- description: QUSB4 0 PHY RX 1 clock source
|
||||
- description: QUSB4 1 PHY RX 0 clock source
|
||||
- description: QUSB4 1 PHY RX 1 clock source
|
||||
- description: QUSB4 2 PHY RX 0 clock source
|
||||
- description: QUSB4 2 PHY RX 1 clock source
|
||||
- description: UFS PHY RX Symbol 0 clock source
|
||||
- description: UFS PHY RX Symbol 1 clock source
|
||||
- description: UFS PHY TX Symbol 0 clock source
|
||||
- description: USB3 PHY 0 pipe clock source
|
||||
- description: USB3 PHY 1 pipe clock source
|
||||
- description: USB3 PHY 2 pipe clock source
|
||||
- description: USB3 UNI PHY pipe 0 clock source
|
||||
- description: USB3 UNI PHY pipe 1 clock source
|
||||
- description: USB4 PHY 0 pcie pipe clock source
|
||||
- description: USB4 PHY 0 Max pipe clock source
|
||||
- description: USB4 PHY 1 pcie pipe clock source
|
||||
- description: USB4 PHY 1 Max pipe clock source
|
||||
- description: USB4 PHY 2 pcie pipe clock source
|
||||
- description: USB4 PHY 2 Max pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,glymur-gcc";
|
||||
reg = <0x100000 0x1f9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&usb_0_phy_dp0_gmux>,
|
||||
<&usb_0_phy_dp1_gmux>,
|
||||
<&usb_0_phy_pcie_pipegmux>,
|
||||
<&usb_0_phy_pipegmux>,
|
||||
<&usb_0_phy_sys_pcie_pipegmux>,
|
||||
<&usb_1_phy_dp0_gmux_2>,
|
||||
<&usb_1_phy_dp1_gmux_2>,
|
||||
<&usb_1_phy_pcie_pipegmux>,
|
||||
<&usb_1_phy_pipegmux>,
|
||||
<&usb_1_phy_sys_pcie_pipegmux>,
|
||||
<&usb_2_phy_dp0_gmux 2>,
|
||||
<&usb_2_phy_dp1_gmux 2>,
|
||||
<&usb_2_phy_pcie_pipegmux>,
|
||||
<&usb_2_phy_pipegmux>,
|
||||
<&usb_2_phy_sys_pcie_pipegmux>,
|
||||
<&pcie_3a_pipe>, <&pcie_3b_pipe>,
|
||||
<&pcie_4_pipe>, <&pcie_5_pipe>,
|
||||
<&pcie_6_pipe>,
|
||||
<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
|
||||
<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
|
||||
<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
|
||||
<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
|
||||
<&ufs_phy_tx_symbol_0>,
|
||||
<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
|
||||
<&usb3_phy_2_pipe>,
|
||||
<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
|
||||
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
|
||||
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
|
||||
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -17,6 +17,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-rpmh-clk
|
||||
- qcom,milos-rpmh-clk
|
||||
- qcom,qcs615-rpmh-clk
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
|
|
|
|||
|
|
@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
|
|||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm TCSR clock control module provides the clocks, resets and
|
||||
power domains on SM8550
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,glymur-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
|
||||
|
|
@ -22,6 +24,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,glymur-tcsr
|
||||
- qcom,milos-tcsr
|
||||
- qcom,sar2130p-tcsr
|
||||
- qcom,sm8550-tcsr
|
||||
|
|
|
|||
|
|
@ -23,13 +23,17 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm6350-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm6350-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
- items:
|
||||
- const: qcom,sc8180x-videocc
|
||||
- const: qcom,sm8150-videocc
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
|
@ -110,8 +114,9 @@ allOf:
|
|||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8150-videocc
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8150-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-peric1
|
||||
- samsung,exynos990-cmu-peric0
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-peris
|
||||
- samsung,exynos990-cmu-top
|
||||
|
|
@ -56,6 +58,28 @@ required:
|
|||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-peric1
|
||||
- samsung,exynos990-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
|
||||
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s2mpg10-clk
|
||||
- samsung,s2mps11-clk
|
||||
- samsung,s2mps13-clk # S2MPS13 and S2MPS15
|
||||
- samsung,s2mps14-clk
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
Binding for Silicon Labs 514 programmable I2C clock generator.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the device can be
|
||||
found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si514 datasheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be "silabs,si514"
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si514".
|
||||
|
||||
Example:
|
||||
si514: clock-generator@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si514";
|
||||
};
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
|
||||
i2c clock generator.
|
||||
|
||||
Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
[3] Si5345 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
|
||||
|
||||
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
||||
The internal structure of the clock generators can be found in [2].
|
||||
The Si5345 is similar to the Si5341 with the addition of fractional input
|
||||
dividers and automatic input selection, as described in [3].
|
||||
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
|
||||
|
||||
The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
configured when the driver probes, it assumes the driver must fully initialize
|
||||
it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
The driver currently does not support any fancy input configurations. They can
|
||||
still be programmed into the chip and the driver will leave them "as is".
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of the following:
|
||||
"silabs,si5340" - Si5340 A/B/C/D
|
||||
"silabs,si5341" - Si5341 A/B/C/D
|
||||
"silabs,si5342" - Si5342 A/B/C/D
|
||||
"silabs,si5344" - Si5344 A/B/C/D
|
||||
"silabs,si5345" - Si5345 A/B/C/D
|
||||
- reg: i2c device address, usually 0x74
|
||||
- #clock-cells: from common clock binding; shall be set to 2.
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
The second value is the output or synthesizer index.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
corresponding to inputs. Use a fixed clock for the "xtal" input.
|
||||
At least one must be present.
|
||||
- clock-names: One of: "xtal", "in0", "in1", "in2"
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: Regulator node for VDD
|
||||
- vdda-supply: Regulator node for VDDA
|
||||
- vdds-supply: Regulator node for VDDS
|
||||
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
|
||||
feedback divider. Must be such that the PLL output is in the valid range. For
|
||||
example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
|
||||
the fraction matters, using 3500 and 12 will deliver the exact same result.
|
||||
If these are not specified, and the PLL is not yet programmed when the driver
|
||||
probes, the PLL will be set to 14GHz.
|
||||
- silabs,reprogram: When present, the driver will always assume the device must
|
||||
be initialized, and always performs the soft-reset routine. Since this will
|
||||
temporarily stop all output clocks, don't do this if the chip is generating
|
||||
the CPU clock for example.
|
||||
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
|
||||
in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
|
||||
- interrupts: Interrupt for INTRb pin.
|
||||
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
|
||||
rather than 1.8V thresholds.
|
||||
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
|
||||
specified output. The driver selects the output VDD_SEL setting based on this
|
||||
voltage.
|
||||
- #address-cells: shall be set to 1.
|
||||
- #size-cells: shall be set to 0.
|
||||
|
||||
|
||||
== Child nodes: Outputs ==
|
||||
|
||||
The child nodes list the output clocks.
|
||||
|
||||
Each of the clock outputs can be overwritten individually by using a child node.
|
||||
If a child node for a clock output is not set, the configuration remains
|
||||
unchanged.
|
||||
|
||||
Required child node properties:
|
||||
- reg: number of clock output.
|
||||
|
||||
Optional child node properties:
|
||||
- silabs,format: Output format, one of:
|
||||
1 = differential (defaults to LVDS levels)
|
||||
2 = low-power (defaults to HCSL levels)
|
||||
4 = LVCMOS
|
||||
- silabs,common-mode: Manually override output common mode, see [2] for values
|
||||
- silabs,amplitude: Manually override output amplitude, see [2] for values
|
||||
- silabs,synth-master: boolean. If present, this output is allowed to change the
|
||||
multisynth frequency dynamically.
|
||||
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
|
||||
when disabled, otherwise it's driven LOW.
|
||||
|
||||
==Example==
|
||||
|
||||
/* 48MHz reference crystal */
|
||||
ref48: ref48M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c-master-node {
|
||||
/* Programmable clock (for logic) */
|
||||
si5341: clock-generator@74 {
|
||||
reg = <0x74>;
|
||||
compatible = "silabs,si5341";
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
|
||||
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
|
||||
silabs,pll-m-den = <48>;
|
||||
silabs,reprogram; /* Chips are not programmed, always reset */
|
||||
|
||||
out@0 {
|
||||
reg = <0>;
|
||||
silabs,format = <1>; /* LVDS 3v3 */
|
||||
silabs,common-mode = <3>;
|
||||
silabs,amplitude = <3>;
|
||||
silabs,synth-master;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 6 configuration:
|
||||
* LVDS 1v8
|
||||
*/
|
||||
out@6 {
|
||||
reg = <6>;
|
||||
silabs,format = <1>; /* LVDS 1v8 */
|
||||
silabs,common-mode = <13>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 8 configuration:
|
||||
* HCSL 3v3
|
||||
*/
|
||||
out@8 {
|
||||
reg = <8>;
|
||||
silabs,format = <2>;
|
||||
silabs,common-mode = <11>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
some-video-node {
|
||||
/* Standard clock bindings */
|
||||
clock-names = "pixel";
|
||||
clocks = <&si5341 0 7>; /* Output 7 */
|
||||
|
||||
/* Set output 7 to use syntesizer 3 as its parent */
|
||||
assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
|
||||
assigned-clock-parents = <&si5341 1 3>;
|
||||
/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
|
||||
assigned-clock-rates = <148500000>, <594000000>;
|
||||
};
|
||||
|
||||
some-audio-node {
|
||||
clock-names = "i2s-clk";
|
||||
clocks = <&si5341 0 0>;
|
||||
/*
|
||||
* since output 0 is a synth-master, the synth will be automatically set
|
||||
* to an appropriate frequency when the audio driver requests another
|
||||
* frequency. We give control over synth 2 to this output here.
|
||||
*/
|
||||
assigned-clocks = <&si5341 0 0>;
|
||||
assigned-clock-parents = <&si5341 1 2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/silabs,si5341.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
|
||||
|
||||
maintainers:
|
||||
- Mike Looijmans <mike.looijmans@topic.nl>
|
||||
|
||||
description: >
|
||||
Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
|
||||
generator.
|
||||
|
||||
Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
[3] Si5345 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
|
||||
|
||||
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
||||
The internal structure of the clock generators can be found in [2].
|
||||
The Si5345 is similar to the Si5341 with the addition of fractional input
|
||||
dividers and automatic input selection, as described in [3].
|
||||
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
|
||||
|
||||
The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
configured when the driver probes, it assumes the driver must fully initialize
|
||||
it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silabs,si5340
|
||||
- silabs,si5341
|
||||
- silabs,si5342
|
||||
- silabs,si5344
|
||||
- silabs,si5345
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
description: >
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
|
||||
The second value is the output or synthesizer index.
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xtal
|
||||
- const: in0
|
||||
- const: in1
|
||||
- const: in2
|
||||
|
||||
clock-output-names: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: Interrupt for INTRb pin
|
||||
|
||||
vdd-supply:
|
||||
description: Regulator node for VDD
|
||||
|
||||
vdda-supply:
|
||||
description: Regulator node for VDDA
|
||||
|
||||
vdds-supply:
|
||||
description: Regulator node for VDDS
|
||||
|
||||
silabs,pll-m-num:
|
||||
description:
|
||||
Numerator for PLL feedback divider. Must be such that the PLL output is in
|
||||
the valid range. For example, to create 14GHz from a 48MHz xtal, use
|
||||
m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12
|
||||
will deliver the exact same result. If these are not specified, and the
|
||||
PLL is not yet programmed when the driver probes, the PLL will be set to
|
||||
14GHz.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,pll-m-den:
|
||||
description: Denominator for PLL feedback divider
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,reprogram:
|
||||
description: Always perform soft-reset and reinitialize PLL
|
||||
type: boolean
|
||||
|
||||
silabs,xaxb-ext-clk:
|
||||
description: Use XA/XB pins as external reference clock
|
||||
type: boolean
|
||||
|
||||
silabs,iovdd-33:
|
||||
description: I2C lines use 3.3V thresholds
|
||||
type: boolean
|
||||
|
||||
patternProperties:
|
||||
"^vddo[0-9]-supply$": true
|
||||
|
||||
"^out@[0-9]$":
|
||||
description: >
|
||||
Output-specific override nodes
|
||||
|
||||
Each of the clock outputs can be overwritten individually by using a child
|
||||
node. If a child node for a clock output is not set, the configuration
|
||||
remains unchanged.
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: Number of clock output
|
||||
maximum: 9
|
||||
|
||||
always-on:
|
||||
description: Set to keep the clock output always running
|
||||
type: boolean
|
||||
|
||||
silabs,format:
|
||||
description: Output format
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 4]
|
||||
|
||||
silabs,common-mode:
|
||||
description: Override output common mode
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,amplitude:
|
||||
description: Override output amplitude
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,synth-master:
|
||||
description: Allow dynamic multisynth rate control
|
||||
type: boolean
|
||||
|
||||
silabs,disable-high:
|
||||
description: Drive output HIGH when disabled
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-generator@74 {
|
||||
reg = <0x74>;
|
||||
compatible = "silabs,si5341";
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
|
||||
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
|
||||
silabs,pll-m-den = <48>;
|
||||
silabs,reprogram; /* Chips are not programmed, always reset */
|
||||
|
||||
out@0 {
|
||||
reg = <0>;
|
||||
silabs,format = <1>; /* LVDS 3v3 */
|
||||
silabs,common-mode = <3>;
|
||||
silabs,amplitude = <3>;
|
||||
silabs,synth-master;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 6 configuration:
|
||||
* LVDS 1v8
|
||||
*/
|
||||
out@6 {
|
||||
reg = <6>;
|
||||
silabs,format = <1>; /* LVDS 1v8 */
|
||||
silabs,common-mode = <13>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 8 configuration:
|
||||
* HCSL 3v3
|
||||
*/
|
||||
out@8 {
|
||||
reg = <8>;
|
||||
silabs,format = <2>;
|
||||
silabs,common-mode = <11>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
Binding for Silicon Labs 544 programmable I2C clock generator.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the device can be
|
||||
found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si544 datasheet
|
||||
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
|
||||
to the speed grade of the chip.
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si544".
|
||||
|
||||
Example:
|
||||
si544: clock-controller@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si544b";
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/silabs,si544.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Labs SI514/SI544 clock generator
|
||||
|
||||
maintainers:
|
||||
- Mike Looijmans <mike.looijmans@topic.nl>
|
||||
|
||||
description: >
|
||||
Silicon Labs 514/544 programmable I2C clock generator. Details about the device
|
||||
can be found in the datasheet:
|
||||
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silabs,si514
|
||||
- silabs,si544a
|
||||
- silabs,si544b
|
||||
- silabs,si544c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si544b";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
Binding for Silicon Labs 570, 571, 598 and 599 programmable
|
||||
I2C clock generators.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the devices can be
|
||||
found in the data sheets[2][3].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si570/571 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
|
||||
[3] Si598/599 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be one of "silabs,si570", "silabs,si571",
|
||||
"silabs,si598", "silabs,si599"
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
- factory-fout: Factory set default frequency. This frequency is part specific.
|
||||
The correct frequency for the part used has to be provided in
|
||||
order to generate the correct output frequencies. For more
|
||||
details, please refer to the data sheet.
|
||||
- temperature-stability: Temperature stability of the device in PPM. Should be
|
||||
one of: 7, 20, 50 or 100.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si570".
|
||||
- clock-frequency: Output frequency to generate. This defines the output
|
||||
frequency set during boot. It can be reprogrammed during
|
||||
runtime through the common clock framework.
|
||||
- silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
|
||||
on hardware loading of RAM from NVM at power on.
|
||||
|
||||
Example:
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/silabs,si570.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Labs Si570/Si571/Si598/Si599 programmable I2C clock generator
|
||||
|
||||
maintainers:
|
||||
- Soren Brinkmann <soren.brinkmann@xilinx.com>
|
||||
|
||||
description: >
|
||||
Silicon Labs 570, 571, 598 and 599 programmable I2C clock generators. Details
|
||||
about the devices can be found in the data sheets[1][2].
|
||||
|
||||
[1] Si570/571 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
|
||||
[2] Si598/599 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silabs,si570
|
||||
- silabs,si571
|
||||
- silabs,si598
|
||||
- silabs,si599
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
factory-fout:
|
||||
description: Factory-set default frequency in Hz.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
temperature-stability:
|
||||
description: Temperature stability of the device in PPM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum:
|
||||
- 7
|
||||
- 20
|
||||
- 50
|
||||
- 100
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
description: Output frequency to generate at boot; can be reprogrammed at runtime.
|
||||
|
||||
silabs,skip-recall:
|
||||
description: Skip the NVM-to-RAM recall operation during boot.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- factory-fout
|
||||
- temperature-stability
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-generator@5d {
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
#clock-cells = <0>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STM32MP21 Reset Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
|
||||
|
||||
description: |
|
||||
The RCC hardware block is both a reset and a clock controller.
|
||||
RCC makes also power management (resume/suspend).
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/st,stm32mp21-rcc.h
|
||||
include/dt-bindings/reset/st,stm32mp21-rcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32mp21-rcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
|
||||
- description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
|
||||
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
|
||||
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
|
||||
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
|
||||
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
|
||||
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
|
||||
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
|
||||
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
|
||||
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
|
||||
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
|
||||
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
|
||||
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
|
||||
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
|
||||
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
|
||||
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
|
||||
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
|
||||
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
|
||||
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
|
||||
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
|
||||
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
|
||||
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
|
||||
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
|
||||
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
|
||||
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
|
||||
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
|
||||
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
|
||||
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
|
||||
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
|
||||
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
|
||||
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
|
||||
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
|
||||
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
|
||||
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
|
||||
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
|
||||
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
|
||||
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
|
||||
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
|
||||
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
|
||||
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
|
||||
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
|
||||
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
|
||||
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
|
||||
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
|
||||
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
|
||||
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
|
||||
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
|
||||
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
|
||||
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
|
||||
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
|
||||
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
|
||||
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
|
||||
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
|
||||
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
|
||||
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
|
||||
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
|
||||
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
|
||||
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
|
||||
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
|
||||
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
|
||||
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
|
||||
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
|
||||
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
|
||||
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
|
||||
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
|
||||
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
|
||||
- description: CK_SCMI_ICN_APB5 Peripheral bridge 5
|
||||
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
|
||||
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
|
||||
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
|
||||
|
||||
clock-controller@44200000 {
|
||||
compatible = "st,stm32mp21-rcc";
|
||||
reg = <0x44200000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_MSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>,
|
||||
<&scmi_clk CK_SCMI_HSE_DIV2>,
|
||||
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
|
||||
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
|
||||
<&scmi_clk CK_SCMI_ICN_SDMMC>,
|
||||
<&scmi_clk CK_SCMI_ICN_DDR>,
|
||||
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
|
||||
<&scmi_clk CK_SCMI_ICN_HSL>,
|
||||
<&scmi_clk CK_SCMI_ICN_NIC>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_07>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_08>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_09>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_10>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_11>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_12>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_13>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_14>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_16>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_17>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_18>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_19>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_20>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_21>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_22>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_23>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_24>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_25>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_26>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_27>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_29>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_30>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_31>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_33>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_36>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_37>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_38>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_39>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_40>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_41>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_42>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_43>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_44>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_45>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_46>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_47>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_48>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_50>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_51>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_52>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_53>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_54>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_55>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_56>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_57>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_58>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_61>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_62>,
|
||||
<&scmi_clk CK_SCMI_FLEXGEN_63>,
|
||||
<&scmi_clk CK_SCMI_ICN_APB1>,
|
||||
<&scmi_clk CK_SCMI_ICN_APB2>,
|
||||
<&scmi_clk CK_SCMI_ICN_APB3>,
|
||||
<&scmi_clk CK_SCMI_ICN_APB4>,
|
||||
<&scmi_clk CK_SCMI_ICN_APB5>,
|
||||
<&scmi_clk CK_SCMI_ICN_APBDBG>,
|
||||
<&scmi_clk CK_SCMI_TIMG1>,
|
||||
<&scmi_clk CK_SCMI_TIMG2>;
|
||||
};
|
||||
...
|
||||
|
|
@ -11,9 +11,9 @@ maintainers:
|
|||
|
||||
description: |
|
||||
The RCC hardware block is both a reset and a clock controller.
|
||||
RCC makes also power management (resume/supend).
|
||||
RCC makes also power management (resume/suspend).
|
||||
|
||||
See also::
|
||||
See also:
|
||||
include/dt-bindings/clock/st,stm32mp25-rcc.h
|
||||
include/dt-bindings/reset/st,stm32mp25-rcc.h
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ properties:
|
|||
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
|
||||
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
|
||||
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
|
||||
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
|
||||
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
|
||||
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
|
||||
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
|
||||
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
|
||||
|
|
@ -108,15 +108,14 @@ properties:
|
|||
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
|
||||
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
|
||||
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
|
||||
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
|
||||
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
|
||||
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
|
||||
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
|
||||
- description: CK_SCMI_PLL3 PLL3 clock
|
||||
- description: clk_dsi_txbyte DSI byte clock
|
||||
|
||||
access-controllers:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -131,7 +130,7 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
|
||||
|
||||
rcc: clock-controller@44200000 {
|
||||
clock-controller@44200000 {
|
||||
compatible = "st,stm32mp25-rcc";
|
||||
reg = <0x44200000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -64,12 +64,9 @@ Required properties:
|
|||
audio use case)
|
||||
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
|
||||
and activate synchronous mode)
|
||||
"st,flexgen-stih407-a0"
|
||||
"st,flexgen-stih410-a0"
|
||||
"st,flexgen-stih407-c0"
|
||||
"st,flexgen-stih410-c0"
|
||||
"st,flexgen-stih418-c0"
|
||||
"st,flexgen-stih407-d0"
|
||||
"st,flexgen-stih410-d0"
|
||||
"st,flexgen-stih407-d2"
|
||||
"st,flexgen-stih418-d2"
|
||||
|
|
|
|||
|
|
@ -18,10 +18,17 @@ maintainers:
|
|||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra20-apbdma
|
||||
- enum:
|
||||
- nvidia,tegra114-apbdma
|
||||
- nvidia,tegra20-apbdma
|
||||
- items:
|
||||
- const: nvidia,tegra30-apbdma
|
||||
- const: nvidia,tegra20-apbdma
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra124-apbdma
|
||||
- nvidia,tegra210-apbdma
|
||||
- const: nvidia,tegra148-apbdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -32,6 +39,9 @@ properties:
|
|||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: dma
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Should contain all of the per-channel DMA interrupts in
|
||||
|
|
|
|||
|
|
@ -21,6 +21,11 @@ properties:
|
|||
- renesas,r9a08g045-dmac # RZ/G3S
|
||||
- const: renesas,rz-dmac
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a09g047-dmac # RZ/G3E
|
||||
- const: renesas,r9a09g057-dmac
|
||||
|
||||
- const: renesas,r9a09g057-dmac # RZ/V2H(P)
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/spacemit,k1-pdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 PDMA Controller
|
||||
|
||||
maintainers:
|
||||
- Guodong Xu <guodong@riscstar.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-pdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Shared interrupt for all DMA channels
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dma-channels:
|
||||
maximum: 16
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description:
|
||||
The DMA request number for the peripheral device.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- dma-channels
|
||||
- '#dma-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/spacemit,k1-syscon.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dma-controller@d4000000 {
|
||||
compatible = "spacemit,k1-pdma";
|
||||
reg = <0x0 0xd4000000 0x0 0x4000>;
|
||||
interrupts = <72>;
|
||||
clocks = <&syscon_apmu CLK_DMA>;
|
||||
resets = <&syscon_apmu RESET_DMA>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -109,26 +109,3 @@ axi_vdma_0: axivdma@40030000 {
|
|||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel. For MCMDA, MM2S channel(write/tx) ID start from
|
||||
'0' and is in [0-15] range. S2MM channel(read/rx) ID start
|
||||
from '16' and is in [16-31] range. These channels ID are
|
||||
fixed irrespective of IP configuration.
|
||||
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
vdmatest_0: vdmatest@0 {
|
||||
compatible ="xlnx,axi-vdma-test-1.00.a";
|
||||
dmas = <&axi_vdma_0 0
|
||||
&axi_vdma_0 1>;
|
||||
dma-names = "vdma0", "vdma1";
|
||||
} ;
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ properties:
|
|||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Total eeprom size in bytes.
|
||||
Also used for FRAMs without device ID where the size cannot be detected.
|
||||
|
||||
address-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
|
@ -146,4 +147,11 @@ examples:
|
|||
reg = <1>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
|
||||
fram@2 {
|
||||
compatible = "cypress,fm25", "atmel,at25";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <20000000>;
|
||||
size = <2048>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/eeprom/st,m24lr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics M24LR NFC/RFID EEPROM
|
||||
|
||||
maintainers:
|
||||
- Abd-Alrhman Masalkhi <abd.masalkhi@gmail.com>
|
||||
|
||||
description:
|
||||
STMicroelectronics M24LR series are dual-interface (RF + I2C)
|
||||
EEPROM chips. These devices support I2C-based access to both
|
||||
memory and a system area that controls authentication and configuration.
|
||||
They expose two I2C addresses, one for the system parameter sector and
|
||||
one for the EEPROM.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/nvmem/nvmem.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,m24lr04e-r
|
||||
- st,m24lr16e-r
|
||||
- st,m24lr64e-r
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: I2C address used for control/system registers
|
||||
- description: I2C address used for EEPROM memory access
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "st,m24lr04e-r";
|
||||
reg = <0x57>, /* primary-device */
|
||||
<0x53>; /* secondary-device */
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
|
||||
* Richtek RT8973A - Micro USB Switch device
|
||||
|
||||
The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
|
||||
is a USB port accessory detector and switch that is optimized to protect low
|
||||
voltage system from abnormal high input voltage (up to 28V) and supports high
|
||||
speed USB operation. Also, RT8973A support 'auto-configuration' mode.
|
||||
If auto-configuration mode is enabled, RT8973A would control internal h/w patch
|
||||
for USB D-/D+ switching.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "richtek,rt8973a-muic"
|
||||
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
|
||||
- interrupts: Interrupt specifiers for detection interrupt sources.
|
||||
|
||||
Example:
|
||||
|
||||
rt8973a@14 {
|
||||
compatible = "richtek,rt8973a-muic";
|
||||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 0>;
|
||||
reg = <0x14>;
|
||||
};
|
||||
|
|
@ -25,6 +25,12 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- id-gpios
|
||||
- required:
|
||||
- vbus-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/extcon/maxim,max14526.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Maxim MAX14526 MicroUSB Integrated Circuit (MUIC)
|
||||
|
||||
maintainers:
|
||||
- Svyatoslav Ryhel <clamor95@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: maxim,max14526
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
connector:
|
||||
$ref: /schemas/connector/usb-connector.yaml#
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- connector
|
||||
- port
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
muic@44 {
|
||||
compatible = "maxim,max14526";
|
||||
reg = <0x44>;
|
||||
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <72 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-b-connector";
|
||||
label = "micro-USB";
|
||||
type = "micro";
|
||||
};
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
muic_to_charger: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&charger_input>;
|
||||
};
|
||||
|
||||
muic_to_usb: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&usb_input>;
|
||||
};
|
||||
|
||||
muic_to_mhl: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&mhl_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/extcon/richtek,rt8973a-muic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Richtek RT8973A MUIC
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
|
||||
description:
|
||||
The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
|
||||
is a USB port accessory detector and switch that is optimized to protect low
|
||||
voltage system from abnormal high input voltage (up to 28V) and supports high
|
||||
speed USB operation. Also, RT8973A support 'auto-configuration' mode.
|
||||
If auto-configuration mode is enabled, RT8973A would control internal h/w patch
|
||||
for USB D-/D+ switching.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: richtek,rt8973a-muic
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
usb-switch@14 {
|
||||
compatible = "richtek,rt8973a-muic";
|
||||
reg = <0x14>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/apm,xgene-slimpro-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene SLIMpro Mailbox I2C
|
||||
|
||||
maintainers:
|
||||
- Khuong Dinh <khuong@os.amperecomputing.com>
|
||||
|
||||
description:
|
||||
An I2C controller accessed over the "SLIMpro" mailbox.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: apm,xgene-slimpro-i2c
|
||||
|
||||
mboxes:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
compatible = "apm,xgene-slimpro-i2c";
|
||||
mboxes = <&mailbox 0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/hisilicon,hix5hd2-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: I2C for HiSilicon hix5hd2 chipset platform
|
||||
|
||||
maintainers:
|
||||
- Wei Yan <sledge.yanwei@huawei.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- hisilicon,hix5hd2-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
description: Desired I2C bus frequency in Hz
|
||||
default: 100000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/hix5hd2-clock.h>
|
||||
|
||||
i2c@f8b10000 {
|
||||
compatible = "hisilicon,hix5hd2-i2c";
|
||||
reg = <0xf8b10000 0x1000>;
|
||||
interrupts = <0 38 4>;
|
||||
clocks = <&clock HIX5HD2_I2C0_RST>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
I2C for Hisilicon hix5hd2 chipset platform
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "hisilicon,hix5hd2-i2c"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- clocks: phandles to input clocks.
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
|
||||
- Child nodes conforming to i2c bus binding
|
||||
|
||||
Examples:
|
||||
I2C0@f8b10000 {
|
||||
compatible = "hisilicon,hix5hd2-i2c";
|
||||
reg = <0xf8b10000 0x1000>;
|
||||
interrupts = <0 38 4>;
|
||||
clocks = <&clock HIX5HD2_I2C0_RST>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
}
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
APM X-Gene SLIMpro Mailbox I2C Driver
|
||||
|
||||
An I2C controller accessed over the "SLIMpro" mailbox.
|
||||
|
||||
Required properties :
|
||||
|
||||
- compatible : should be "apm,xgene-slimpro-i2c"
|
||||
- mboxes : use the label reference for the mailbox as the first parameter.
|
||||
The second parameter is the channel number.
|
||||
|
||||
Example :
|
||||
i2cslimpro {
|
||||
compatible = "apm,xgene-slimpro-i2c";
|
||||
mboxes = <&mailbox 0>;
|
||||
};
|
||||
|
|
@ -10,9 +10,11 @@ maintainers:
|
|||
- Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
|
||||
description:
|
||||
The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which
|
||||
RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which
|
||||
if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be
|
||||
assigned to either I2C controller.
|
||||
RTL9310 SoCs have equal capabilities but support 12 common SDA lines which
|
||||
can be assigned to either I2C controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -23,11 +25,19 @@ properties:
|
|||
- realtek,rtl9302c-i2c
|
||||
- realtek,rtl9303-i2c
|
||||
- const: realtek,rtl9301-i2c
|
||||
- const: realtek,rtl9301-i2c
|
||||
- items:
|
||||
- enum:
|
||||
- realtek,rtl9311-i2c
|
||||
- realtek,rtl9312-i2c
|
||||
- realtek,rtl9313-i2c
|
||||
- const: realtek,rtl9310-i2c
|
||||
- enum:
|
||||
- realtek,rtl9301-i2c
|
||||
- realtek,rtl9310-i2c
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Register offset and size this I2C controller.
|
||||
- description: Register offset and size of this I2C controller.
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
|
@ -35,19 +45,44 @@ properties:
|
|||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
realtek,scl:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The SCL line number of this I2C controller.
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
patternProperties:
|
||||
'^i2c@[0-7]$':
|
||||
'^i2c@[0-9ab]$':
|
||||
$ref: /schemas/i2c/i2c-controller.yaml
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: The SDA pin associated with the I2C bus.
|
||||
description: The SDA line number associated with the I2C bus.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: realtek,rtl9310-i2c
|
||||
then:
|
||||
required:
|
||||
- realtek,scl
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: realtek,rtl9301-i2c
|
||||
then:
|
||||
patternProperties:
|
||||
'^i2c@[89ab]$': false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: ADIS16240 Programmable Impact Sensor and Recorder driver
|
||||
|
||||
maintainers:
|
||||
- Alexandru Tachici <alexandru.tachici@analog.com>
|
||||
- Marcelo Schmitt <marcelo.schmitt@analog.com>
|
||||
- Nuno Sá <nuno.sa@analog.com>
|
||||
|
||||
description: |
|
||||
ADIS16240 Programmable Impact Sensor and Recorder driver that supports
|
||||
|
|
@ -37,7 +38,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -73,7 +72,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -72,7 +71,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -74,7 +73,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer
|
||||
|
||||
maintainers:
|
||||
- Stefan Popa <stefan.popa@analog.com>
|
||||
- Marcelo Schmitt <marcelo.schmitt@analog.com>
|
||||
- Nuno Sá <nuno.sa@analog.com>
|
||||
|
||||
description: |
|
||||
Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer that supports
|
||||
|
|
@ -37,7 +38,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -52,7 +52,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -107,7 +107,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
# include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ examples:
|
|||
};
|
||||
};
|
||||
- |
|
||||
# include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -93,7 +93,6 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Analog Devices AD7124 ADC device driver
|
||||
|
||||
maintainers:
|
||||
- Stefan Popa <stefan.popa@analog.com>
|
||||
- Marcelo Schmitt <marcelo.schmitt@analog.com>
|
||||
- Nuno Sá <nuno.sa@analog.com>
|
||||
|
||||
description: |
|
||||
Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
|
||||
|
|
@ -27,12 +28,21 @@ properties:
|
|||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: phandle to the master clock (mclk)
|
||||
description: Optional external clock connected to the CLK pin.
|
||||
|
||||
clock-names:
|
||||
deprecated: true
|
||||
description:
|
||||
MCLK is an internal counter in the ADC. Do not use this property.
|
||||
items:
|
||||
- const: mclk
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
The CLK pin can be used as an output. When that is the case, include
|
||||
this property.
|
||||
const: 0
|
||||
|
||||
interrupts:
|
||||
description: IRQ line for the ADC
|
||||
maxItems: 1
|
||||
|
|
@ -66,10 +76,14 @@ properties:
|
|||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
|
||||
# Can't have both clock input and output at the same time.
|
||||
not:
|
||||
required:
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
|
||||
patternProperties:
|
||||
"^channel@([0-9]|1[0-5])$":
|
||||
$ref: adc.yaml
|
||||
|
|
@ -135,8 +149,6 @@ examples:
|
|||
interrupt-parent = <&gpio>;
|
||||
rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
|
||||
refin1-supply = <&adc_vref>;
|
||||
clocks = <&ad7124_mclk>;
|
||||
clock-names = "mclk";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -379,7 +379,6 @@ unevaluatedProperties: false
|
|||
examples:
|
||||
# Example AD7173-8 with external reference connected to REF+/REF-:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
spi {
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ properties:
|
|||
- adi,ad7910
|
||||
- adi,ad7920
|
||||
- adi,ad7940
|
||||
- rohm,bd79105
|
||||
- ti,adc081s
|
||||
- ti,adc101s
|
||||
- ti,adc121s
|
||||
|
|
@ -55,6 +56,11 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
The data-ready interrupt. Provided via DOUT pin.
|
||||
maxItems: 1
|
||||
|
||||
vcc-supply:
|
||||
description:
|
||||
Main powersupply voltage for the chips, sometimes referred to as VDD on
|
||||
|
|
@ -75,6 +81,10 @@ properties:
|
|||
description: A GPIO used to trigger the start of a conversion
|
||||
maxItems: 1
|
||||
|
||||
rdy-gpios:
|
||||
description: A GPIO for detecting the data-ready.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -82,6 +92,20 @@ required:
|
|||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
# Devices with an IRQ
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
interrupts: true
|
||||
else:
|
||||
properties:
|
||||
interrupts: false
|
||||
|
||||
# Devices where reference is vcc
|
||||
- if:
|
||||
properties:
|
||||
|
|
@ -106,19 +130,18 @@ allOf:
|
|||
- vcc-supply
|
||||
# Devices with a vref
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7091r
|
||||
- adi,ad7273
|
||||
- adi,ad7274
|
||||
- adi,ad7475
|
||||
- lltc,ltc2314-14
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7091r
|
||||
- adi,ad7273
|
||||
- adi,ad7274
|
||||
- adi,ad7475
|
||||
- lltc,ltc2314-14
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
vref-supply: true
|
||||
else:
|
||||
properties:
|
||||
vref-supply: false
|
||||
# Devices with a vref where it is not optional
|
||||
|
|
@ -131,35 +154,58 @@ allOf:
|
|||
- adi,ad7274
|
||||
- adi,ad7475
|
||||
- lltc,ltc2314-14
|
||||
- rohm,bd79105
|
||||
then:
|
||||
required:
|
||||
- vref-supply
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7475
|
||||
- adi,ad7495
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7475
|
||||
- adi,ad7495
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
vdrive-supply: true
|
||||
else:
|
||||
properties:
|
||||
vdrive-supply: false
|
||||
|
||||
# Devices which support polling the data-ready via GPIO
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
rdy-gpios: false
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7091
|
||||
- adi,ad7091r
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
adi,conversion-start-gpios: false
|
||||
|
||||
# Devices with a convstart GPIO where it is not optional
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- adi,ad7091
|
||||
- adi,ad7091r
|
||||
- rohm,bd79105
|
||||
then:
|
||||
properties:
|
||||
adi,conversion-start-gpios: true
|
||||
else:
|
||||
properties:
|
||||
adi,conversion-start-gpios: false
|
||||
required:
|
||||
- adi,conversion-start-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -80,11 +80,36 @@ properties:
|
|||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
io-backends:
|
||||
maxItems: 1
|
||||
|
||||
adi,num-lanes:
|
||||
description:
|
||||
Number of lanes on which the data is sent on the output when the data
|
||||
output interface is used.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 4]
|
||||
default: 4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
not:
|
||||
required:
|
||||
- io-backends
|
||||
then:
|
||||
properties:
|
||||
adi,num-lanes: false
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- interrupts
|
||||
- required:
|
||||
- io-backends
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
@ -107,4 +132,21 @@ examples:
|
|||
clocks = <&adc_clk>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
adc@0 {
|
||||
compatible = "adi,ad7779";
|
||||
reg = <0>;
|
||||
start-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio0 93 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&adc_clk>;
|
||||
io-backends = <&iio_backend>;
|
||||
adi,num-lanes = <4>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue