mirror of https://github.com/torvalds/linux.git
irqchip/gic-v3: Drop support for custom PPI partitions
The only thing getting in the way of correctly handling PPIs the way they were intended is the GICv3 hack that deals with PPI partitions. Remove that code, allowing the common code to kick in. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Will Deacon <will@kernel.org> Link: https://patch.msgid.link/20251020122944.3074811-22-maz@kernel.org
This commit is contained in:
Marc Zyngier
Thomas Gleixner
parent
4cdf4813f5
commit
64b9738eaa
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@ -36,7 +36,6 @@ config GIC_NON_BANKED
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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select HAVE_ARM_SMCCC_DISCOVERY
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select IRQ_MSI_IOMMU
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@ -26,7 +26,6 @@
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/irqchip/arm-gic-v3-prio.h>
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#include <linux/irqchip/irq-partition-percpu.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/arm-smccc.h>
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@ -46,8 +45,6 @@ static u8 dist_prio_nmi __ro_after_init = GICV3_PRIO_NMI;
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#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2)
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#define FLAGS_WORKAROUND_INSECURE (1ULL << 3)
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#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
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static struct cpumask broken_rdists __read_mostly __maybe_unused;
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struct redist_region {
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@ -68,11 +65,15 @@ struct gic_chip_data {
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u64 flags;
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bool has_rss;
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unsigned int ppi_nr;
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struct partition_desc **ppi_descs;
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struct partition_affinity *parts;
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unsigned int nr_parts;
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};
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struct partition_affinity {
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cpumask_t mask;
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struct fwnode_handle *partition_id;
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};
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#define T241_CHIPS_MAX 4
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static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;
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static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);
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@ -593,18 +594,6 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
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writeb_relaxed(prio, base + offset + index);
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}
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static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
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{
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switch (__get_intid_range(hwirq)) {
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case PPI_RANGE:
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return hwirq - 16;
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case EPPI_RANGE:
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return hwirq - EPPI_BASE_INTID + 16;
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default:
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unreachable();
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}
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}
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static int gic_irq_nmi_setup(struct irq_data *d)
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{
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struct irq_desc *desc = irq_to_desc(d->irq);
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@ -1628,13 +1617,6 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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case GIC_IRQ_TYPE_LPI: /* LPI */
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*hwirq = fwspec->param[1];
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break;
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case GIC_IRQ_TYPE_PARTITION:
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*hwirq = fwspec->param[1];
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if (fwspec->param[1] >= 16)
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*hwirq += EPPI_BASE_INTID - 16;
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else
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*hwirq += 16;
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break;
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default:
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return -EINVAL;
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}
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@ -1643,10 +1625,8 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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/*
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* Make it clear that broken DTs are... broken.
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* Partitioned PPIs are an unfortunate exception.
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*/
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WARN_ON(*type == IRQ_TYPE_NONE &&
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fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
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WARN_ON(*type == IRQ_TYPE_NONE);
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return 0;
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}
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@ -1703,33 +1683,12 @@ static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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}
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}
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static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
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irq_hw_number_t hwirq)
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{
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enum gic_intid_range range;
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if (!gic_data.ppi_descs)
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return false;
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if (!is_of_node(fwspec->fwnode))
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return false;
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if (fwspec->param_count < 4 || !fwspec->param[3])
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return false;
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range = __get_intid_range(hwirq);
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if (range != PPI_RANGE && range != EPPI_RANGE)
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return false;
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return true;
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}
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static int gic_irq_domain_select(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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enum irq_domain_bus_token bus_token)
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{
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unsigned int type, ppi_idx;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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/* Not for us */
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@ -1748,15 +1707,7 @@ static int gic_irq_domain_select(struct irq_domain *d,
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if (WARN_ON_ONCE(ret))
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return 0;
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if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
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return d == gic_data.domain;
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/*
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* If this is a PPI and we have a 4th (non-null) parameter,
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* then we need to match the partition domain.
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*/
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ppi_idx = __gic_get_ppi_index(hwirq);
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return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
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}
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static int gic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_fwspec_info *info)
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@ -1813,45 +1764,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
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.get_fwspec_info = gic_irq_get_fwspec_info,
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};
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static int partition_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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unsigned long ppi_intid;
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struct device_node *np;
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unsigned int ppi_idx;
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int ret;
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if (!gic_data.ppi_descs)
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return -ENOMEM;
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np = of_find_node_by_phandle(fwspec->param[3]);
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if (WARN_ON(!np))
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return -EINVAL;
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ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
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if (WARN_ON_ONCE(ret))
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return 0;
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ppi_idx = __gic_get_ppi_index(ppi_intid);
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ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
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of_fwnode_handle(np));
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if (ret < 0)
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return ret;
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*hwirq = ret;
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static const struct irq_domain_ops partition_domain_ops = {
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.translate = partition_domain_translate,
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.select = gic_irq_domain_select,
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.get_fwspec_info = gic_irq_get_fwspec_info,
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};
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static bool gic_enable_quirk_msm8996(void *data)
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{
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struct gic_chip_data *d = data;
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@ -2174,12 +2086,7 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
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if (!parts_node)
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return;
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gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
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if (!gic_data.ppi_descs)
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goto out_put_node;
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nr_parts = of_get_child_count(parts_node);
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if (!nr_parts)
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goto out_put_node;
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@ -2235,30 +2142,6 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
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gic_data.parts = parts;
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gic_data.nr_parts = nr_parts;
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for (i = 0; i < gic_data.ppi_nr; i++) {
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unsigned int irq;
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struct partition_desc *desc;
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struct irq_fwspec ppi_fwspec = {
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.fwnode = gic_data.fwnode,
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.param_count = 3,
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.param = {
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[0] = GIC_IRQ_TYPE_PARTITION,
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[1] = i,
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[2] = IRQ_TYPE_NONE,
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},
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};
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irq = irq_create_fwspec_mapping(&ppi_fwspec);
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if (WARN_ON(!irq))
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continue;
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desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
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irq, &partition_domain_ops);
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if (WARN_ON(!desc))
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continue;
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gic_data.ppi_descs[i] = desc;
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}
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out_put_node:
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of_node_put(parts_node);
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}
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