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drm/msm/adreno: Expose a PARAM to check AQE support 

AQE (Applicaton Qrisc Engine) is required to support VK ray-pipeline. Two
conditions should be met to use this HW:
  1. AQE firmware should be loaded and programmed
  2. Preemption support

Expose a new MSM_PARAM to allow userspace to query its support.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714685/
Message-ID: <20260327-a8xx-gpu-batch2-v2-17-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen 2026-03-27 05:44:06 +05:30 committed by Rob Clark
parent 7fad33097e
commit 64ac64bb62
4 changed files with 19 additions and 0 deletions
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13
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -2604,6 +2604,17 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
return 0;
}
static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu)
{
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
/*
* AQE uses preemption context record as scratch pad, so check if
* preemption is enabled
*/
return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo;
}
static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
@ -2803,6 +2814,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
.bus_halt = a6xx_bus_clear_pending_transactions,
.mmu_fault_handler = a6xx_fault_handler,
.gx_is_on = a7xx_gmu_gx_is_on,
.aqe_is_enabled = a6xx_aqe_is_enabled,
};
const struct adreno_gpu_funcs a8xx_gpu_funcs = {
@ -2831,4 +2843,5 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
.bus_halt = a8xx_bus_clear_pending_transactions,
.mmu_fault_handler = a8xx_fault_handler,
.gx_is_on = a8xx_gmu_gx_is_on,
.aqe_is_enabled = a6xx_aqe_is_enabled,
};

4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -441,6 +441,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
case MSM_PARAM_HAS_PRR:
*value = adreno_smmu_has_prr(gpu);
return 0;
case MSM_PARAM_AQE:
*value = !!(adreno_gpu->funcs->aqe_is_enabled &&
adreno_gpu->funcs->aqe_is_enabled(adreno_gpu));
return 0;
default:
return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
}

1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@ -80,6 +80,7 @@ struct adreno_gpu_funcs {
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
bool (*gx_is_on)(struct adreno_gpu *adreno_gpu);
bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu);
};
struct adreno_reglist {

1
include/uapi/drm/msm_drm.h
View File

@ -117,6 +117,7 @@ struct drm_msm_timespec {
* ioctl will throw -EPIPE.
*/
#define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */
#define MSM_PARAM_AQE 0x17 /* RO */
/* For backwards compat. The original support for preemption was based on
* a single ring per priority level so # of priority levels equals the #