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dt-bindings: clock: qcom: document the Milos Display Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Luca Weiss
Bjorn Andersson
parent
f003800e2d
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on Milos
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maintainers:
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- Luca Weiss <luca.weiss@fairphone.com>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on Milos.
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See also: include/dt-bindings/clock/qcom,milos-dispcc.h
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properties:
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compatible:
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const: qcom,milos-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: Display's AHB clock
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Link clock from DP PHY0
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- description: VCO DIV clock from DP PHY0
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,milos-gcc.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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clock-controller@af00000 {
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compatible = "qcom,milos-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&bi_tcxo_div2>,
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<&sleep_clk>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -0,0 +1,61 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_ACCU_CLK 1
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#define DISP_CC_MDSS_AHB1_CLK 2
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#define DISP_CC_MDSS_AHB_CLK 3
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#define DISP_CC_MDSS_AHB_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_CLK 5
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 8
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 9
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10
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#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 12
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20
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#define DISP_CC_MDSS_ESC0_CLK 21
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#define DISP_CC_MDSS_ESC0_CLK_SRC 22
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#define DISP_CC_MDSS_MDP1_CLK 23
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#define DISP_CC_MDSS_MDP_CLK 24
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#define DISP_CC_MDSS_MDP_CLK_SRC 25
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#define DISP_CC_MDSS_MDP_LUT1_CLK 26
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#define DISP_CC_MDSS_MDP_LUT_CLK 27
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28
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#define DISP_CC_MDSS_PCLK0_CLK 29
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 30
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#define DISP_CC_MDSS_RSCC_AHB_CLK 31
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 32
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#define DISP_CC_MDSS_VSYNC1_CLK 33
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#define DISP_CC_MDSS_VSYNC_CLK 34
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 35
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#define DISP_CC_SLEEP_CLK 36
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#define DISP_CC_SLEEP_CLK_SRC 37
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#define DISP_CC_XO_CLK 38
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#define DISP_CC_XO_CLK_SRC 39
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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#endif
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