mirror of https://github.com/torvalds/linux.git
Documentation: gpio: Add a compatibility and feature list for PCA953x
I went through all the datasheets and created this note listing chip functions and register layouts. Signed-off-by: Levente Révész <levente.revesz@eilabs.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20251112224924.2091880-1-andriy.shevchenko@linux.intel.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Levente Révész
Bartosz Golaszewski
parent
8ad236f8a4
commit
5ef5f3c224
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@ -15,6 +15,7 @@ Contents:
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legacy-boards
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drivers-on-gpio
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bt8xxgpio
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pca953x
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Core
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====
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@ -0,0 +1,552 @@
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============================================
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PCA953x I²C GPIO expander compatibility list
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============================================
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:Author: Levente Révész <levente.revesz@eilabs.com>
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I went through all the datasheets and created this note listing
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chip functions and register layouts.
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Overview of chips
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=================
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Chips with the basic 4 registers
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--------------------------------
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These chips have 4 register banks: input, output, invert and direction.
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Each of these banks contains (lines/8) registers, one for each GPIO port.
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Banks offset is always a power of 2:
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- 4 lines -> bank offset is 1
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- 8 lines -> bank offset is 1
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- 16 lines -> bank offset is 2
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- 24 lines -> bank offset is 4
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- 32 lines -> bank offset is 4
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- 40 lines -> bank offset is 8
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For example, register layout of GPIO expander with 24 lines:
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+------+-----------------+--------+
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| addr | function | bank |
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+======+=================+========+
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| 00 | input port0 | |
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+------+-----------------+ |
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| 01 | input port1 | bank 0 |
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+------+-----------------+ |
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| 02 | input port2 | |
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+------+-----------------+--------+
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| 03 | n/a | |
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+------+-----------------+--------+
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| 04 | output port0 | |
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+------+-----------------+ |
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| 05 | output port1 | bank 1 |
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+------+-----------------+ |
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| 06 | output port2 | |
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+------+-----------------+--------+
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| 07 | n/a | |
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+------+-----------------+--------+
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| 08 | invert port0 | |
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+------+-----------------+ |
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| 09 | invert port1 | bank 2 |
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+------+-----------------+ |
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| 0A | invert port2 | |
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+------+-----------------+--------+
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| 0B | n/a | |
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+------+-----------------+--------+
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| 0C | direction port0 | |
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+------+-----------------+ |
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| 0D | direction port1 | bank 3 |
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+------+-----------------+ |
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| 0E | direction port2 | |
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+------+-----------------+--------+
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| 0F | n/a | |
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+------+-----------------+--------+
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.. note::
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This is followed by all supported chips, except by pcal6534.
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The table below shows the offsets for each of the compatible chips:
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========== ===== ========= ===== ====== ====== =========
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compatible lines interrupt input output invert direction
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========== ===== ========= ===== ====== ====== =========
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pca9536 4 no 00 01 02 03
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pca9537 4 yes 00 01 02 03
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pca6408 8 yes 00 01 02 03
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tca6408 8 yes 00 01 02 03
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pca9534 8 yes 00 01 02 03
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pca9538 8 yes 00 01 02 03
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pca9554 8 yes 00 01 02 03
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tca9554 8 yes 00 01 02 03
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pca9556 8 no 00 01 02 03
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pca9557 8 no 00 01 02 03
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pca6107 8 yes 00 01 02 03
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pca6416 16 yes 00 02 04 06
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tca6416 16 yes 00 02 04 06
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pca9535 16 yes 00 02 04 06
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pca9539 16 yes 00 02 04 06
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tca9539 16 yes 00 02 04 06
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pca9555 16 yes 00 02 04 06
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max7318 16 yes 00 02 04 06
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tca6424 24 yes 00 04 08 0C
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========== ===== ========= ===== ====== ====== =========
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Chips with additional timeout_en register
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-----------------------------------------
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These Maxim chips have a bus timeout function which can be enabled in
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the timeout_en register. This is present in only two chips. Defaults to
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timeout disabled.
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========== ===== ========= ===== ====== ====== ========= ==========
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compatible lines interrupt input output invert direction timeout_en
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========== ===== ========= ===== ====== ====== ========= ==========
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max7310 8 no 00 01 02 03 04
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max7312 16 yes 00 02 04 06 08
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========== ===== ========= ===== ====== ====== ========= ==========
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Chips with additional int_mask register
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---------------------------------------
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These chips have an interrupt mask register in addition to the 4 basic
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registers. The interrupt masks default to all interrupts disabled. To
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use interrupts with these chips, the driver has to set the int_mask
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register.
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========== ===== ========= ===== ====== ====== ========= ========
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compatible lines interrupt input output invert direction int_mask
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========== ===== ========= ===== ====== ====== ========= ========
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pca9505 40 yes 00 08 10 18 20
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pca9506 40 yes 00 08 10 18 20
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========== ===== ========= ===== ====== ====== ========= ========
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Chips with additional int_mask and out_conf registers
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-----------------------------------------------------
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This chip has an interrupt mask register, and an output port
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configuration register, which can select between push-pull and
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open-drain modes. Each bit controls two lines. Both of these registers
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are present in PCAL chips as well, albeit the out_conf works
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differently.
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========== ===== ========= ===== ====== ====== ========= ======== ========
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compatible lines interrupt input output invert direction int_mask out_conf
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========== ===== ========= ===== ====== ====== ========= ======== ========
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pca9698 40 yes 00 08 10 18 20 28
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========== ===== ========= ===== ====== ====== ========= ======== ========
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pca9698 also has a "master output" register for setting all outputs per
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port to the same value simultaneously, and a chip specific mode register
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for various additional chip settings.
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========== ============= ====
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compatible master_output mode
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========== ============= ====
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pca9698 29 2A
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========== ============= ====
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Chips with LED blink and intensity control
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------------------------------------------
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These Maxim chips have no invert register.
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They have two sets of output registers (output0 and output1). An internal
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timer alternates the effective output between the values set in these
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registers, if blink mode is enabled in the blink register. The
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master_intensity register and the intensity registers together define
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the PWM intensity value for each pair of outputs.
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These chips can be used as simple GPIO expanders if the driver handles the
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input, output0 and direction registers.
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========== ===== ========= ===== ======= ========= ======= ================ ===== =========
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compatible lines interrupt input output0 direction output1 master_intensity blink intensity
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========== ===== ========= ===== ======= ========= ======= ================ ===== =========
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max7315 8 yes 00 01 03 09 0E 0F 10
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max7313 16 yes 00 02 06 0A 0E 0F 10
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========== ===== ========= ===== ======= ========= ======= ================ ===== =========
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Basic PCAL chips
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----------------
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========== ===== ========= ===== ====== ====== =========
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compatible lines interrupt input output invert direction
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========== ===== ========= ===== ====== ====== =========
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pcal6408 8 yes 00 01 02 03
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pcal9554b 8 yes 00 01 02 03
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pcal6416 16 yes 00 02 04 06
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pcal9535 16 yes 00 02 04 06
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pcal9555a 16 yes 00 02 04 06
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========== ===== ========= ===== ====== ====== =========
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These chips have several additional features:
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1. output drive strength setting (out_strength)
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2. input latch (in_latch)
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3. pull-up/pull-down (pull_in, pull_sel)
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4. push-pull/open-drain outputs (out_conf)
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5. interrupt mask and interrupt status (int_mask, int_status)
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========== ============ ======== ======= ======== ======== ========== ========
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compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf
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========== ============ ======== ======= ======== ======== ========== ========
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pcal6408 40 42 43 44 45 46 4F
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pcal9554b 40 42 43 44 45 46 4F
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pcal6416 40 44 46 48 4A 4C 4F
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pcal9535 40 44 46 48 4A 4C 4F
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pcal9555a 40 44 46 48 4A 4C 4F
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========== ============ ======== ======= ======== ======== ========== ========
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Currently the driver has support for the input latch, pull-up/pull-down
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and uses int_mask and int_status for interrupts.
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PCAL chips with extended interrupt and output configuration functions
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---------------------------------------------------------------------
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========== ===== ========= ===== ====== ====== =========
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compatible lines interrupt input output invert direction
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========== ===== ========= ===== ====== ====== =========
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pcal6524 24 yes 00 04 08 0C
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pcal6534 34 yes 00 05 0A 0F
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========== ===== ========= ===== ====== ====== =========
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These chips have the full PCAL register set, plus the following functions:
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1. interrupt event selection: level, rising, falling, any edge
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2. clear interrupt status per line
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3. read input without clearing interrupt status
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4. individual output config (push-pull/open-drain) per output line
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5. debounce inputs
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========== ============ ======== ======= ======== ======== ========== ========
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compatible out_strength in_latch pull_en pull_sel int_mask int_status out_conf
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========== ============ ======== ======= ======== ======== ========== ========
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pcal6524 40 48 4C 50 54 58 5C
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pcal6534 30 3A 3F 44 49 4E 53
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========== ============ ======== ======= ======== ======== ========== ========
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========== ======== ========= ============ ============== ======== ==============
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compatible int_edge int_clear input_status indiv_out_conf debounce debounce_count
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========== ======== ========= ============ ============== ======== ==============
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pcal6524 60 68 6C 70 74 76
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pcal6534 54 5E 63 68 6D 6F
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========== ======== ========= ============ ============== ======== ==============
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As can be seen in the table above, pcal6534 does not follow the usual
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bank spacing rule. Its banks are closely packed instead.
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PCA957X chips with a completely different register layout
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---------------------------------------------------------
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These chips have the basic 4 registers, but at unusual addresses.
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Additionally, they have:
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1. pull-up/pull-down (pull_sel)
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2. a global pull enable, defaults to disabled (config)
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3. interrupt mask, interrupt status (int_mask, int_status)
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========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ==========
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compatible lines interrupt input invert config pull_sel direction output int_mask int_status
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========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ==========
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pca9574 8 yes 00 01 02 03 04 05 06 07
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pca9575 16 yes 00 02 04 06 08 0A 0C 0E
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========== ===== ========= ===== ====== ====== ======== ========= ====== ======== ==========
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Currently the driver supports none of the advanced features.
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XRA1202
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-------
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Basic 4 registers, plus advanced features:
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1. interrupt mask, defaults to interrupts disabled
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2. interrupt status
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3. interrupt event selection, level, rising, falling, any edge
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(int_mask, rising_mask, falling_mask)
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4. pull-up (no pull-down)
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5. tri-state
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6. debounce
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========== ===== ========= ===== ====== ====== ========= =========
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compatible lines interrupt input output invert direction pullup_en
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========== ===== ========= ===== ====== ====== ========= =========
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xra1202 8 yes 00 01 02 03 04
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========== ===== ========= ===== ====== ====== ========= =========
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========== ======== ======== ========== =========== ============ ========
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compatible int_mask tristate int_status rising_mask falling_mask debounce
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========== ======== ======== ========== =========== ============ ========
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xra1202 05 06 07 08 09 0A
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========== ======== ======== ========== =========== ============ ========
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Overview of functions
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=====================
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This section lists chip functions that are supported by the driver
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already, or are at least common in multiple chips.
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Input, Output, Invert, Direction
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--------------------------------
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The basic 4 GPIO functions are present in all but one chip category, i.e.
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`Chips with LED blink and intensity control`_ are missing the invert
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register.
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3 different layouts are used for these registers:
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1. banks 0, 1, 2, 3 with bank offsets of 2^n
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- all other chips
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2. banks 0, 1, 2, 3 with closely packed banks
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- pcal6534
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3. banks 0, 5, 1, 4 with bank offsets of 2^n
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- pca9574
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- pca9575
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Interrupts
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----------
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Only an interrupt mask register
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The same layout is used for all of these:
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1. bank 5 with bank offsets of 2^n
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- pca9505
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- pca9506
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- pca9698
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Interrupt mask and interrupt status registers
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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These work the same way in all of the chips: mask and status have
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one bit per line, 1 in the mask means interrupt enabled.
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Layouts:
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1. base offset 0x40, bank 5 and bank 6, bank offsets of 2^n
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- pcal6408
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- pcal6416
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- pcal9535
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- pcal9554b
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- pcal9555a
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- pcal6524
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2. base offset 0x30, bank 5 and 6, closely packed banks
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- pcal6534
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3. bank 6 and 7, bank offsets of 2^n
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- pca9574
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- pca9575
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4. bank 5 and 7, bank offsets of 2^n
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- xra1202
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Interrupt on specific edges
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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`PCAL chips with extended interrupt and output configuration functions`_
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have an int_edge register. This contains 2 bits per line, one of 4 events
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can be selected for each line:
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0: level, 1: rising edge, 2: falling edge, 3: any edge
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Layouts:
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1. base offset 0x40, bank 7, bank offsets of 2^n
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- pcal6524
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2. base offset 0x30, bank 7 + offset 0x01, closely packed banks
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(out_conf is 1 byte, not (lines/8) bytes, hence the 0x01 offset)
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- pcal6534
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`XRA1202`_ chips have a different mechanism for the same thing: they have
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a rising mask and a falling mask, with one bit per line.
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Layout:
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1. bank 5, bank offsets of 2^n
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Input latch
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-----------
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Only `Basic PCAL chips`_ and
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`PCAL chips with extended interrupt and output configuration functions`_
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have this function. When the latch is enabled, the interrupt is not cleared
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until the input port is read. When the latch is disabled, the interrupt
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is cleared even if the input register is not read, if the input pin returns
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to the logic value it had before generating the interrupt. Defaults to latch
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disabled.
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Currently the driver enables the latch for each line with interrupt
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enabled.
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1. base offset 0x40, bank 2, bank offsets of 2^n
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- pcal6408
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- pcal6416
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- pcal9535
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- pcal9554b
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- pcal9555a
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- pcal6524
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2. base offset 0x30, bank 2, closely packed banks
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- pcal6534
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Pull-up and pull-down
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---------------------
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`Basic PCAL chips`_ and
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`PCAL chips with extended interrupt and output configuration functions`_
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use the same mechanism: their pull_en register enables the pull-up or pull-down
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function, and their pull_sel register chooses the direction. They all use one
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bit per line.
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0: pull-down, 1: pull-up
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Layouts:
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1. base offset 0x40, bank 3 (en) and 4 (sel), bank offsets of 2^n
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- pcal6408
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- pcal6416
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- pcal9535
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- pcal9554b
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- pcal9555a
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- pcal6524
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2. base offset 0x30, bank 3 (en) and 4 (sel), closely packed banks
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- pcal6534
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`PCA957X chips with a completely different register layout`_ have a pull_sel
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register with one bit per line, and a global pull_en bit in their config
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register.
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Layout:
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1. bank 2 (config), bank 3 (sel), bank offsets of 2^n
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- pca9574
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- pca9575
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`XRA1202`_ chips can only pull-up. They have a pullup_en register.
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Layout:
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1. bank 4, bank offsets of 2^n
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- xra1202
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Push-pull and open-drain
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------------------------
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`Chips with additional int_mask and out_conf registers`_ have this function,
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but only for select IO ports. Register has 1 bit per 2 lines. In pca9698,
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only port0 and port1 have this function.
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0: open-drain, 1: push-pull
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Layout:
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1. base offset 5*bankoffset
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- pca9698
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`Basic PCAL chips`_ have 1 bit per port in one single out_conf register.
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Only whole ports can be configured.
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0: push-pull, 1: open-drain
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Layout:
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1. base offset 0x4F
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- pcal6408
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- pcal6416
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- pcal9535
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- pcal9554b
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- pcal9555a
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`PCAL chips with extended interrupt and output configuration functions`_
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can set this for each line individually. They have the same per-port out_conf
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register as `Basic PCAL chips`_, but they also have an indiv_out_conf register
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with one bit per line, which inverts the effect of the port-wise setting.
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0: push-pull, 1: open-drain
|
||||
|
||||
Layouts:
|
||||
|
||||
1. base offset 0x40 + 7*bankoffset (out_conf),
|
||||
base offset 0x60, bank 4 (indiv_out_conf) with bank offset of 2^n
|
||||
|
||||
- pcal6524
|
||||
|
||||
2. base offset 0x30 + 7*banksize (out_conf),
|
||||
base offset 0x54, bank 4 (indiv_out_conf), closely packed banks
|
||||
|
||||
- pcal6534
|
||||
|
||||
This function is currently not supported by the driver.
|
||||
|
||||
Output drive strength
|
||||
---------------------
|
||||
|
||||
Only PCAL chips have this function. 2 bits per line.
|
||||
|
||||
==== ==============
|
||||
bits drive strength
|
||||
==== ==============
|
||||
00 0.25x
|
||||
01 0.50x
|
||||
10 0.75x
|
||||
11 1.00x
|
||||
==== ==============
|
||||
|
||||
1. base offset 0x40, bank 0 and 1, bank offsets of 2^n
|
||||
- pcal6408
|
||||
- pcal6416
|
||||
- pcal9535
|
||||
- pcal9554b
|
||||
- pcal9555a
|
||||
- pcal6524
|
||||
|
||||
2. base offset 0x30, bank 0 and 1, closely packed banks
|
||||
- pcal6534
|
||||
|
||||
Currently not supported by the driver.
|
||||
|
||||
Datasheets
|
||||
==========
|
||||
|
||||
- MAX7310: https://datasheets.maximintegrated.com/en/ds/MAX7310.pdf
|
||||
- MAX7312: https://datasheets.maximintegrated.com/en/ds/MAX7312.pdf
|
||||
- MAX7313: https://datasheets.maximintegrated.com/en/ds/MAX7313.pdf
|
||||
- MAX7315: https://datasheets.maximintegrated.com/en/ds/MAX7315.pdf
|
||||
- MAX7318: https://datasheets.maximintegrated.com/en/ds/MAX7318.pdf
|
||||
- PCA6107: https://pdf1.alldatasheet.com/datasheet-pdf/view/161780/TI/PCA6107.html
|
||||
- PCA6408A: https://www.nxp.com/docs/en/data-sheet/PCA6408A.pdf
|
||||
- PCA6416A: https://www.nxp.com/docs/en/data-sheet/PCA6416A.pdf
|
||||
- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf
|
||||
- PCA9505: https://www.nxp.com/docs/en/data-sheet/PCA9505_9506.pdf
|
||||
- PCA9534: https://www.nxp.com/docs/en/data-sheet/PCA9534.pdf
|
||||
- PCA9535: https://www.nxp.com/docs/en/data-sheet/PCA9535_PCA9535C.pdf
|
||||
- PCA9536: https://www.nxp.com/docs/en/data-sheet/PCA9536.pdf
|
||||
- PCA9537: https://www.nxp.com/docs/en/data-sheet/PCA9537.pdf
|
||||
- PCA9538: https://www.nxp.com/docs/en/data-sheet/PCA9538.pdf
|
||||
- PCA9539: https://www.nxp.com/docs/en/data-sheet/PCA9539_PCA9539R.pdf
|
||||
- PCA9554: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
|
||||
- PCA9555: https://www.nxp.com/docs/en/data-sheet/PCA9555.pdf
|
||||
- PCA9556: https://www.nxp.com/docs/en/data-sheet/PCA9556.pdf
|
||||
- PCA9557: https://www.nxp.com/docs/en/data-sheet/PCA9557.pdf
|
||||
- PCA9574: https://www.nxp.com/docs/en/data-sheet/PCA9574.pdf
|
||||
- PCA9575: https://www.nxp.com/docs/en/data-sheet/PCA9575.pdf
|
||||
- PCA9698: https://www.nxp.com/docs/en/data-sheet/PCA9698.pdf
|
||||
- PCAL6408A: https://www.nxp.com/docs/en/data-sheet/PCAL6408A.pdf
|
||||
- PCAL6416A: https://www.nxp.com/docs/en/data-sheet/PCAL6416A.pdf
|
||||
- PCAL6524: https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
|
||||
- PCAL6534: https://www.nxp.com/docs/en/data-sheet/PCAL6534.pdf
|
||||
- PCAL9535A: https://www.nxp.com/docs/en/data-sheet/PCAL9535A.pdf
|
||||
- PCAL9554B: https://www.nxp.com/docs/en/data-sheet/PCAL9554B_PCAL9554C.pdf
|
||||
- PCAL9555A: https://www.nxp.com/docs/en/data-sheet/PCAL9555A.pdf
|
||||
- TCA6408A: https://www.ti.com/lit/gpn/tca6408a
|
||||
- TCA6416: https://www.ti.com/lit/gpn/tca6416
|
||||
- TCA6424: https://www.ti.com/lit/gpn/tca6424
|
||||
- TCA9539: https://www.ti.com/lit/gpn/tca9539
|
||||
- TCA9554: https://www.ti.com/lit/gpn/tca9554
|
||||
- XRA1202: https://assets.maxlinear.com/web/documents/xra1202_1202p_101_042213.pdf
|
||||
Loading…
Reference in New Issue