mirror of https://github.com/torvalds/linux.git
PCI: s32g: Add NXP S32G PCIe controller driver (RC)
Add initial support of the PCIe controller for the NXP S32G SoC family. Only host mode is supported. Co-developed-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Signed-off-by: Ionut Vicovan <Ionut.Vicovan@nxp.com> Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> [mani: replaced memblock_start_of_DRAM with hardcoded boundary addr] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251121164920.2008569-4-vincent.guittot@linaro.org
This commit is contained in:
Vincent Guittot
Bjorn Helgaas
parent
045ad2c623
commit
5cbc7d3e31
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@ -256,6 +256,16 @@ config PCIE_TEGRA194_EP
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in order to enable device-specific features PCIE_TEGRA194_EP must be
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selected. This uses the DesignWare core.
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config PCIE_NXP_S32G
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bool "NXP S32G PCIe controller (host mode)"
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depends on ARCH_S32 || COMPILE_TEST
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select PCIE_DW_HOST
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help
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Enable support for the PCIe controller in NXP S32G based boards to
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work in Host mode. The controller is based on DesignWare IP and
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can work either as RC or EP. In order to enable host-specific
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features PCIE_NXP_S32G must be selected.
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config PCIE_DW_PLAT
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bool
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@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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@ -0,0 +1,406 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for NXP S32G SoCs
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*
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* Copyright 2019-2025 NXP
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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/* PCIe controller Sub-System */
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/* PCIe controller 0 General Control 1 */
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#define PCIE_S32G_PE0_GEN_CTRL_1 0x50
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#define DEVICE_TYPE_MASK GENMASK(3, 0)
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#define SRIS_MODE BIT(8)
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/* PCIe controller 0 General Control 3 */
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#define PCIE_S32G_PE0_GEN_CTRL_3 0x58
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#define LTSSM_EN BIT(0)
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/* PCIe Controller 0 Interrupt Status */
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#define PCIE_S32G_PE0_INT_STS 0xE8
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#define HP_INT_STS BIT(6)
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/* Boundary between peripheral space and physical memory space */
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#define S32G_MEMORY_BOUNDARY_ADDR 0x80000000
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struct s32g_pcie_port {
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struct list_head list;
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struct phy *phy;
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};
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struct s32g_pcie {
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struct dw_pcie pci;
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void __iomem *ctrl_base;
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struct list_head ports;
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};
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#define to_s32g_from_dw_pcie(x) \
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container_of(x, struct s32g_pcie, pci)
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static void s32g_pcie_writel_ctrl(struct s32g_pcie *s32g_pp, u32 reg, u32 val)
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{
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writel(val, s32g_pp->ctrl_base + reg);
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}
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static u32 s32g_pcie_readl_ctrl(struct s32g_pcie *s32g_pp, u32 reg)
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{
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return readl(s32g_pp->ctrl_base + reg);
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}
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static void s32g_pcie_enable_ltssm(struct s32g_pcie *s32g_pp)
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{
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u32 reg;
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reg = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3);
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reg |= LTSSM_EN;
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s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3, reg);
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}
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static void s32g_pcie_disable_ltssm(struct s32g_pcie *s32g_pp)
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{
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u32 reg;
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reg = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3);
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reg &= ~LTSSM_EN;
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s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_3, reg);
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}
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static int s32g_pcie_start_link(struct dw_pcie *pci)
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{
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struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
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s32g_pcie_enable_ltssm(s32g_pp);
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return 0;
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}
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static void s32g_pcie_stop_link(struct dw_pcie *pci)
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{
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struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
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s32g_pcie_disable_ltssm(s32g_pp);
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}
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static struct dw_pcie_ops s32g_pcie_ops = {
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.start_link = s32g_pcie_start_link,
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.stop_link = s32g_pcie_stop_link,
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};
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/* Configure the AMBA AXI Coherency Extensions (ACE) interface */
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static void s32g_pcie_reset_mstr_ace(struct dw_pcie *pci)
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{
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u32 ddr_base_low = lower_32_bits(S32G_MEMORY_BOUNDARY_ADDR);
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u32 ddr_base_high = upper_32_bits(S32G_MEMORY_BOUNDARY_ADDR);
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, 0x0);
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/*
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* Ncore is a cache-coherent interconnect module that enables the
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* integration of heterogeneous coherent and non-coherent agents in
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* the chip. Ncore transactions to peripheral should be non-coherent
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* or it might drop them.
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*
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* One example where this is needed are PCIe MSIs, which use NoSnoop=0
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* and might end up routed to Ncore. PCIe coherent traffic (e.g. MSIs)
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* that targets peripheral space will be dropped by Ncore because
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* peripherals on S32G are not coherent as slaves. We add a hard
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* boundary in the PCIe controller coherency control registers to
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* separate physical memory space from peripheral space.
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*
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* Define the start of DDR as seen by Linux as this boundary between
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* "memory" and "peripherals", with peripherals being below.
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*/
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dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_1_OFF,
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(ddr_base_low & CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK));
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dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_2_OFF, ddr_base_high);
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dw_pcie_dbi_ro_wr_dis(pci);
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}
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static int s32g_init_pcie_controller(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct s32g_pcie *s32g_pp = to_s32g_from_dw_pcie(pci);
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u32 val;
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/* Set RP mode */
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val = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1);
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val &= ~DEVICE_TYPE_MASK;
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val |= FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
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/* Use default CRNS */
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val &= ~SRIS_MODE;
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s32g_pcie_writel_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1, val);
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/*
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* Make sure we use the coherency defaults (just in case the settings
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* have been changed from their reset values)
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*/
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s32g_pcie_reset_mstr_ace(pci);
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dw_pcie_dbi_ro_wr_en(pci);
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
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val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
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dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
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val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
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val |= GEN3_RELATED_OFF_EQ_PHASE_2_3;
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dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static const struct dw_pcie_host_ops s32g_pcie_host_ops = {
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.init = s32g_init_pcie_controller,
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};
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static int s32g_init_pcie_phy(struct s32g_pcie *s32g_pp)
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{
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struct dw_pcie *pci = &s32g_pp->pci;
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struct device *dev = pci->dev;
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struct s32g_pcie_port *port, *tmp;
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int ret;
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list_for_each_entry(port, &s32g_pp->ports, list) {
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ret = phy_init(port->phy);
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if (ret) {
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dev_err(dev, "Failed to init serdes PHY\n");
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goto err_phy_revert;
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}
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ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, 0);
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if (ret) {
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dev_err(dev, "Failed to set mode on serdes PHY\n");
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goto err_phy_exit;
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}
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ret = phy_power_on(port->phy);
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if (ret) {
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dev_err(dev, "Failed to power on serdes PHY\n");
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goto err_phy_exit;
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}
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}
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return 0;
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err_phy_exit:
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phy_exit(port->phy);
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err_phy_revert:
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list_for_each_entry_continue_reverse(port, &s32g_pp->ports, list) {
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phy_power_off(port->phy);
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phy_exit(port->phy);
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}
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list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list)
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list_del(&port->list);
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return ret;
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}
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static void s32g_deinit_pcie_phy(struct s32g_pcie *s32g_pp)
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{
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struct s32g_pcie_port *port, *tmp;
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list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list) {
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phy_power_off(port->phy);
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phy_exit(port->phy);
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list_del(&port->list);
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}
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}
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static int s32g_pcie_init(struct device *dev, struct s32g_pcie *s32g_pp)
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{
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s32g_pcie_disable_ltssm(s32g_pp);
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return s32g_init_pcie_phy(s32g_pp);
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}
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static void s32g_pcie_deinit(struct s32g_pcie *s32g_pp)
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{
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s32g_pcie_disable_ltssm(s32g_pp);
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s32g_deinit_pcie_phy(s32g_pp);
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}
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static int s32g_pcie_parse_port(struct s32g_pcie *s32g_pp, struct device_node *node)
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{
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struct device *dev = s32g_pp->pci.dev;
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struct s32g_pcie_port *port;
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int num_lanes;
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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port->phy = devm_of_phy_get(dev, node, NULL);
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if (IS_ERR(port->phy))
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return dev_err_probe(dev, PTR_ERR(port->phy),
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"Failed to get serdes PHY\n");
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INIT_LIST_HEAD(&port->list);
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list_add_tail(&port->list, &s32g_pp->ports);
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/*
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* The DWC core initialization code cannot yet parse the num-lanes
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* attribute in the Root Port node. The S32G only supports one Root
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* Port for now so its driver can parse the node and set the num_lanes
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* field of struct dwc_pcie before calling dw_pcie_host_init().
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*/
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if (!of_property_read_u32(node, "num-lanes", &num_lanes))
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s32g_pp->pci.num_lanes = num_lanes;
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return 0;
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}
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static int s32g_pcie_parse_ports(struct device *dev, struct s32g_pcie *s32g_pp)
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{
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struct s32g_pcie_port *port, *tmp;
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int ret = -ENOENT;
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for_each_available_child_of_node_scoped(dev->of_node, of_port) {
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if (!of_node_is_type(of_port, "pci"))
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continue;
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ret = s32g_pcie_parse_port(s32g_pp, of_port);
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if (ret)
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goto err_port;
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}
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err_port:
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list_for_each_entry_safe(port, tmp, &s32g_pp->ports, list)
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list_del(&port->list);
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return ret;
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}
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static int s32g_pcie_get_resources(struct platform_device *pdev,
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struct s32g_pcie *s32g_pp)
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{
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struct dw_pcie *pci = &s32g_pp->pci;
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struct device *dev = &pdev->dev;
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int ret;
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pci->dev = dev;
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pci->ops = &s32g_pcie_ops;
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s32g_pp->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl");
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if (IS_ERR(s32g_pp->ctrl_base))
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return PTR_ERR(s32g_pp->ctrl_base);
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INIT_LIST_HEAD(&s32g_pp->ports);
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ret = s32g_pcie_parse_ports(dev, s32g_pp);
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if (ret)
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return dev_err_probe(dev, ret,
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"Failed to parse Root Port: %d\n", ret);
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platform_set_drvdata(pdev, s32g_pp);
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return 0;
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}
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static int s32g_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct s32g_pcie *s32g_pp;
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struct dw_pcie_rp *pp;
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int ret;
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s32g_pp = devm_kzalloc(dev, sizeof(*s32g_pp), GFP_KERNEL);
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if (!s32g_pp)
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return -ENOMEM;
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ret = s32g_pcie_get_resources(pdev, s32g_pp);
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if (ret)
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return ret;
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pm_runtime_no_callbacks(dev);
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devm_pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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goto err_pm_runtime_put;
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ret = s32g_pcie_init(dev, s32g_pp);
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if (ret)
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goto err_pm_runtime_put;
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pp = &s32g_pp->pci.pp;
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pp->ops = &s32g_pcie_host_ops;
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pp->use_atu_msg = true;
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ret = dw_pcie_host_init(pp);
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if (ret)
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goto err_pcie_deinit;
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return 0;
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err_pcie_deinit:
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s32g_pcie_deinit(s32g_pp);
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err_pm_runtime_put:
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pm_runtime_put(dev);
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return ret;
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}
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static int s32g_pcie_suspend_noirq(struct device *dev)
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{
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struct s32g_pcie *s32g_pp = dev_get_drvdata(dev);
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struct dw_pcie *pci = &s32g_pp->pci;
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return dw_pcie_suspend_noirq(pci);
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}
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static int s32g_pcie_resume_noirq(struct device *dev)
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{
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struct s32g_pcie *s32g_pp = dev_get_drvdata(dev);
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struct dw_pcie *pci = &s32g_pp->pci;
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return dw_pcie_resume_noirq(pci);
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}
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static const struct dev_pm_ops s32g_pcie_pm_ops = {
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NOIRQ_SYSTEM_SLEEP_PM_OPS(s32g_pcie_suspend_noirq,
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s32g_pcie_resume_noirq)
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};
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static const struct of_device_id s32g_pcie_of_match[] = {
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{ .compatible = "nxp,s32g2-pcie" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, s32g_pcie_of_match);
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static struct platform_driver s32g_pcie_driver = {
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.driver = {
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.name = "s32g-pcie",
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||||
.of_match_table = s32g_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
.pm = pm_sleep_ptr(&s32g_pcie_pm_ops),
|
||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||||
},
|
||||
.probe = s32g_pcie_probe,
|
||||
};
|
||||
|
||||
builtin_platform_driver(s32g_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Ionut Vicovan <Ionut.Vicovan@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP S32G PCIe Host controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue