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iommu/arm-smmu-qcom: Enable use of all SMR groups when running bare-metal 

Some platforms (e.g. SC8280XP and X1E) support more than 128 stream
matching groups. This is more than what is defined as maximum by the ARM
SMMU architecture specification. Commit 1226113473 ("iommu/arm-smmu-qcom:
Limit the SMR groups to 128") disabled use of the additional groups because
they don't exhibit the same behavior as the architecture supported ones.

It seems like this is just another quirk of the hypervisor: When running
bare-metal without the hypervisor, the additional groups appear to behave
just like all others. The boot firmware uses some of the additional groups,
so ignoring them in this situation leads to stream match conflicts whenever
we allocate a new SMR group for the same SID.

The workaround exists primarily because the bypass quirk detection fails
when using a S2CR register from the additional matching groups, so let's
perform the test with the last reliable S2CR (127) and then limit the
number of SMR groups only if we detect that we are running below the
hypervisor (because of the bypass quirk).

Fixes: 1226113473 ("iommu/arm-smmu-qcom: Limit the SMR groups to 128")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Stephan Gerhold 2025-08-21 10:33:53 +02:00 committed by Will Deacon
parent 5941f0e0c1
commit 5583a55e07
1 changed files with 17 additions and 10 deletions
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27
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
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@ -432,17 +432,19 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
/* /*
* Some platforms support more than the Arm SMMU architected maximum of * Some platforms support more than the Arm SMMU architected maximum of
* 128 stream matching groups. For unknown reasons, the additional * 128 stream matching groups. The additional registers appear to have
* groups don't exhibit the same behavior as the architected registers, * the same behavior as the architected registers in the hardware.
* so limit the groups to 128 until the behavior is fixed for the other * However, on some firmware versions, the hypervisor does not
* groups. * correctly trap and emulate accesses to the additional registers,
* resulting in unexpected behavior.
*
* If there are more than 128 groups, use the last reliable group to
* detect if we need to apply the bypass quirk.
*/ */
if (smmu->num_mapping_groups > 128) { if (smmu->num_mapping_groups > 128)
dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n"); last_s2cr = ARM_SMMU_GR0_S2CR(127);
smmu->num_mapping_groups = 128; else
} last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
/* /*
* With some firmware versions writes to S2CR of type FAULT are * With some firmware versions writes to S2CR of type FAULT are
@ -465,6 +467,11 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
if (smmu->num_mapping_groups > 128) {
dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
smmu->num_mapping_groups = 128;
}
} }
for (i = 0; i < smmu->num_mapping_groups; i++) { for (i = 0; i < smmu->num_mapping_groups; i++) {