mirror of https://github.com/torvalds/linux.git
iommupt: Add the Intel VT-d second stage page table format
The VT-d second stage format is almost the same as the x86 PAE format,
except the bit encodings in the PTE are different and a few new PTE
features, like force coherency are present.
Among all the formats it is unique in not having a designated present bit.
Comparing the performance of several operations to the existing version:
iommu_map()
pgsz ,avg new,old ns, min new,old ns , min % (+ve is better)
2^12, 53,66 , 50,64 , 21.21
2^21, 59,70 , 56,67 , 16.16
2^30, 54,66 , 52,63 , 17.17
256*2^12, 384,524 , 337,516 , 34.34
256*2^21, 387,632 , 336,626 , 46.46
256*2^30, 376,629 , 323,623 , 48.48
iommu_unmap()
pgsz ,avg new,old ns, min new,old ns , min % (+ve is better)
2^12, 67,86 , 63,84 , 25.25
2^21, 64,84 , 59,80 , 26.26
2^30, 59,78 , 56,74 , 24.24
256*2^12, 216,335 , 198,317 , 37.37
256*2^21, 245,350 , 232,344 , 32.32
256*2^30, 248,345 , 226,339 , 33.33
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Jason Gunthorpe
Joerg Roedel
parent
efa03dab7c
commit
5448c1558f
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@ -3,6 +3,7 @@ CONFIG_GENERIC_PT=y
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CONFIG_DEBUG_GENERIC_PT=y
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CONFIG_IOMMU_PT=y
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CONFIG_IOMMU_PT_AMDV1=y
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CONFIG_IOMMU_PT_VTDSS=y
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CONFIG_IOMMU_PT_X86_64=y
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CONFIG_IOMMU_PT_KUNIT_TEST=y
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@ -42,6 +42,16 @@ config IOMMU_PT_AMDV1
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_VTDSS
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tristate "IOMMU page table for Intel VT-d Second Stage"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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help
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iommu_domain implementation for the Intel VT-d's 64 bit 3/4/5
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level Second Stage page table. It is similar to the X86_64 format with
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4K/2M/1G page sizes.
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Selected automatically by an IOMMU driver that uses this format.
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config IOMMU_PT_X86_64
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tristate "IOMMU page table for x86 64-bit, 4/5 levels"
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depends on !GENERIC_ATOMIC64 # for cmpxchg64
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@ -57,6 +67,7 @@ config IOMMU_PT_KUNIT_TEST
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depends on KUNIT
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depends on IOMMU_PT_AMDV1 || !IOMMU_PT_AMDV1
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depends on IOMMU_PT_X86_64 || !IOMMU_PT_X86_64
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depends on IOMMU_PT_VTDSS || !IOMMU_PT_VTDSS
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default KUNIT_ALL_TESTS
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help
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Enable kunit tests for GENERIC_PT and IOMMU_PT that covers all the
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@ -3,6 +3,8 @@
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iommu_pt_fmt-$(CONFIG_IOMMU_PT_AMDV1) += amdv1
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iommu_pt_fmt-$(CONFIG_IOMMUFD_TEST) += mock
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iommu_pt_fmt-$(CONFIG_IOMMU_PT_VTDSS) += vtdss
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iommu_pt_fmt-$(CONFIG_IOMMU_PT_X86_64) += x86_64
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IOMMU_PT_KUNIT_TEST :=
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
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*
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*/
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#ifndef __GENERIC_PT_FMT_DEFS_VTDSS_H
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#define __GENERIC_PT_FMT_DEFS_VTDSS_H
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#include <linux/generic_pt/common.h>
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#include <linux/types.h>
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typedef u64 pt_vaddr_t;
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typedef u64 pt_oaddr_t;
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struct vtdss_pt_write_attrs {
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u64 descriptor_bits;
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gfp_t gfp;
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};
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#define pt_write_attrs vtdss_pt_write_attrs
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#endif
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@ -0,0 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
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*/
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#define PT_FMT vtdss
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#define PT_SUPPORTED_FEATURES \
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(BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_VTDSS_FORCE_COHERENCE) | \
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BIT(PT_FEAT_VTDSS_FORCE_WRITEABLE) | BIT(PT_FEAT_DMA_INCOHERENT))
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#include "iommu_template.h"
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@ -0,0 +1,292 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
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*
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* Intel VT-d Second Stange 5/4 level page table
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*
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* This is described in
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* Section "3.7 Second-Stage Translation"
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* Section "9.8 Second-Stage Paging Entries"
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*
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* Of the "Intel Virtualization Technology for Directed I/O Architecture
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* Specification".
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*
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* The named levels in the spec map to the pts->level as:
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* Table/SS-PTE - 0
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* Directory/SS-PDE - 1
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* Directory Ptr/SS-PDPTE - 2
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* PML4/SS-PML4E - 3
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* PML5/SS-PML5E - 4
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*/
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#ifndef __GENERIC_PT_FMT_VTDSS_H
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#define __GENERIC_PT_FMT_VTDSS_H
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#include "defs_vtdss.h"
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#include "../pt_defs.h"
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#include <linux/bitfield.h>
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#include <linux/container_of.h>
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#include <linux/log2.h>
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enum {
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PT_MAX_OUTPUT_ADDRESS_LG2 = 52,
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PT_MAX_VA_ADDRESS_LG2 = 57,
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PT_ITEM_WORD_SIZE = sizeof(u64),
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PT_MAX_TOP_LEVEL = 4,
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PT_GRANULE_LG2SZ = 12,
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PT_TABLEMEM_LG2SZ = 12,
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/* SSPTPTR is 4k aligned and limited by HAW */
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PT_TOP_PHYS_MASK = GENMASK_ULL(63, 12),
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};
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/* Shared descriptor bits */
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enum {
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VTDSS_FMT_R = BIT(0),
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VTDSS_FMT_W = BIT(1),
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VTDSS_FMT_A = BIT(8),
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VTDSS_FMT_D = BIT(9),
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VTDSS_FMT_SNP = BIT(11),
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VTDSS_FMT_OA = GENMASK_ULL(51, 12),
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};
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/* PDPTE/PDE */
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enum {
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VTDSS_FMT_PS = BIT(7),
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};
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#define common_to_vtdss_pt(common_ptr) \
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container_of_const(common_ptr, struct pt_vtdss, common)
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#define to_vtdss_pt(pts) common_to_vtdss_pt((pts)->range->common)
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static inline pt_oaddr_t vtdss_pt_table_pa(const struct pt_state *pts)
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{
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return oalog2_mul(FIELD_GET(VTDSS_FMT_OA, pts->entry),
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PT_TABLEMEM_LG2SZ);
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}
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#define pt_table_pa vtdss_pt_table_pa
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static inline pt_oaddr_t vtdss_pt_entry_oa(const struct pt_state *pts)
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{
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return oalog2_mul(FIELD_GET(VTDSS_FMT_OA, pts->entry),
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PT_GRANULE_LG2SZ);
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}
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#define pt_entry_oa vtdss_pt_entry_oa
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static inline bool vtdss_pt_can_have_leaf(const struct pt_state *pts)
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{
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return pts->level <= 2;
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}
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#define pt_can_have_leaf vtdss_pt_can_have_leaf
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static inline unsigned int vtdss_pt_num_items_lg2(const struct pt_state *pts)
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{
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return PT_TABLEMEM_LG2SZ - ilog2(sizeof(u64));
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}
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#define pt_num_items_lg2 vtdss_pt_num_items_lg2
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static inline enum pt_entry_type vtdss_pt_load_entry_raw(struct pt_state *pts)
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{
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const u64 *tablep = pt_cur_table(pts, u64);
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u64 entry;
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pts->entry = entry = READ_ONCE(tablep[pts->index]);
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if (!entry)
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return PT_ENTRY_EMPTY;
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if (pts->level == 0 ||
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(vtdss_pt_can_have_leaf(pts) && (pts->entry & VTDSS_FMT_PS)))
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return PT_ENTRY_OA;
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return PT_ENTRY_TABLE;
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}
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#define pt_load_entry_raw vtdss_pt_load_entry_raw
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static inline void
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vtdss_pt_install_leaf_entry(struct pt_state *pts, pt_oaddr_t oa,
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unsigned int oasz_lg2,
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const struct pt_write_attrs *attrs)
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{
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u64 *tablep = pt_cur_table(pts, u64);
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u64 entry;
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if (!pt_check_install_leaf_args(pts, oa, oasz_lg2))
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return;
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entry = FIELD_PREP(VTDSS_FMT_OA, log2_div(oa, PT_GRANULE_LG2SZ)) |
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attrs->descriptor_bits;
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if (pts->level != 0)
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entry |= VTDSS_FMT_PS;
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WRITE_ONCE(tablep[pts->index], entry);
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pts->entry = entry;
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}
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#define pt_install_leaf_entry vtdss_pt_install_leaf_entry
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static inline bool vtdss_pt_install_table(struct pt_state *pts,
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pt_oaddr_t table_pa,
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const struct pt_write_attrs *attrs)
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{
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u64 entry;
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entry = VTDSS_FMT_R | VTDSS_FMT_W |
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FIELD_PREP(VTDSS_FMT_OA, log2_div(table_pa, PT_GRANULE_LG2SZ));
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return pt_table_install64(pts, entry);
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}
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#define pt_install_table vtdss_pt_install_table
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static inline void vtdss_pt_attr_from_entry(const struct pt_state *pts,
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struct pt_write_attrs *attrs)
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{
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attrs->descriptor_bits = pts->entry &
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(VTDSS_FMT_R | VTDSS_FMT_W | VTDSS_FMT_SNP);
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}
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#define pt_attr_from_entry vtdss_pt_attr_from_entry
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static inline bool vtdss_pt_entry_is_write_dirty(const struct pt_state *pts)
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{
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u64 *tablep = pt_cur_table(pts, u64) + pts->index;
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return READ_ONCE(*tablep) & VTDSS_FMT_D;
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}
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#define pt_entry_is_write_dirty vtdss_pt_entry_is_write_dirty
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static inline void vtdss_pt_entry_make_write_clean(struct pt_state *pts)
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{
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u64 *tablep = pt_cur_table(pts, u64) + pts->index;
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WRITE_ONCE(*tablep, READ_ONCE(*tablep) & ~(u64)VTDSS_FMT_D);
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}
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#define pt_entry_make_write_clean vtdss_pt_entry_make_write_clean
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static inline bool vtdss_pt_entry_make_write_dirty(struct pt_state *pts)
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{
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u64 *tablep = pt_cur_table(pts, u64) + pts->index;
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u64 new = pts->entry | VTDSS_FMT_D;
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return try_cmpxchg64(tablep, &pts->entry, new);
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}
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#define pt_entry_make_write_dirty vtdss_pt_entry_make_write_dirty
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static inline unsigned int vtdss_pt_max_sw_bit(struct pt_common *common)
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{
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return 10;
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}
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#define pt_max_sw_bit vtdss_pt_max_sw_bit
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static inline u64 vtdss_pt_sw_bit(unsigned int bitnr)
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{
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/* Bits marked Ignored in the specification */
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switch (bitnr) {
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case 0:
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return BIT(10);
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case 1 ... 9:
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return BIT_ULL((bitnr - 1) + 52);
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case 10:
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return BIT_ULL(63);
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/* Some bits in 9-3 are available in some entries */
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default:
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if (__builtin_constant_p(bitnr))
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BUILD_BUG();
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else
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PT_WARN_ON(true);
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return 0;
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}
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}
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#define pt_sw_bit vtdss_pt_sw_bit
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/* --- iommu */
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#include <linux/generic_pt/iommu.h>
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#include <linux/iommu.h>
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#define pt_iommu_table pt_iommu_vtdss
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/* The common struct is in the per-format common struct */
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static inline struct pt_common *common_from_iommu(struct pt_iommu *iommu_table)
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{
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return &container_of(iommu_table, struct pt_iommu_table, iommu)
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->vtdss_pt.common;
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}
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static inline struct pt_iommu *iommu_from_common(struct pt_common *common)
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{
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return &container_of(common, struct pt_iommu_table, vtdss_pt.common)
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->iommu;
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}
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static inline int vtdss_pt_iommu_set_prot(struct pt_common *common,
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struct pt_write_attrs *attrs,
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unsigned int iommu_prot)
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{
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u64 pte = 0;
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/*
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* VTDSS does not have a present bit, so we tell if any entry is present
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* by checking for R or W.
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*/
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if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
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return -EINVAL;
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if (iommu_prot & IOMMU_READ)
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pte |= VTDSS_FMT_R;
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if (iommu_prot & IOMMU_WRITE)
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pte |= VTDSS_FMT_W;
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if (pt_feature(common, PT_FEAT_VTDSS_FORCE_COHERENCE))
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pte |= VTDSS_FMT_SNP;
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if (pt_feature(common, PT_FEAT_VTDSS_FORCE_WRITEABLE) &&
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!(iommu_prot & IOMMU_WRITE)) {
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pr_err_ratelimited(
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"Read-only mapping is disallowed on the domain which serves as the parent in a nested configuration, due to HW errata (ERRATA_772415_SPR17)\n");
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return -EINVAL;
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}
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attrs->descriptor_bits = pte;
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return 0;
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}
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#define pt_iommu_set_prot vtdss_pt_iommu_set_prot
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static inline int vtdss_pt_iommu_fmt_init(struct pt_iommu_vtdss *iommu_table,
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const struct pt_iommu_vtdss_cfg *cfg)
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{
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struct pt_vtdss *table = &iommu_table->vtdss_pt;
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unsigned int vasz_lg2 = cfg->common.hw_max_vasz_lg2;
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if (vasz_lg2 > PT_MAX_VA_ADDRESS_LG2)
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return -EOPNOTSUPP;
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else if (vasz_lg2 > 48)
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pt_top_set_level(&table->common, 4);
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else if (vasz_lg2 > 39)
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pt_top_set_level(&table->common, 3);
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else if (vasz_lg2 > 30)
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pt_top_set_level(&table->common, 2);
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else
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return -EOPNOTSUPP;
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return 0;
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}
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#define pt_iommu_fmt_init vtdss_pt_iommu_fmt_init
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static inline void
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vtdss_pt_iommu_fmt_hw_info(struct pt_iommu_vtdss *table,
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const struct pt_range *top_range,
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struct pt_iommu_vtdss_hw_info *info)
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{
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info->ssptptr = virt_to_phys(top_range->top_table);
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PT_WARN_ON(info->ssptptr & ~PT_TOP_PHYS_MASK);
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/*
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* top_level = 2 = 3 level table aw=1
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* top_level = 3 = 4 level table aw=2
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* top_level = 4 = 5 level table aw=3
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*/
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info->aw = top_range->top_level - 1;
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}
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#define pt_iommu_fmt_hw_info vtdss_pt_iommu_fmt_hw_info
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#if defined(GENERIC_PT_KUNIT)
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static const struct pt_iommu_vtdss_cfg vtdss_kunit_fmt_cfgs[] = {
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[0] = { .common.hw_max_vasz_lg2 = 39 },
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[1] = { .common.hw_max_vasz_lg2 = 48 },
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[2] = { .common.hw_max_vasz_lg2 = 57 },
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};
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#define kunit_fmt_cfgs vtdss_kunit_fmt_cfgs
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enum { KUNIT_FMT_FEATURES = BIT(PT_FEAT_VTDSS_FORCE_WRITEABLE) };
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#endif
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#endif
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@ -157,6 +157,24 @@ enum {
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PT_FEAT_AMDV1_FORCE_COHERENCE,
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};
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struct pt_vtdss {
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struct pt_common common;
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};
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enum {
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/*
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* The PTEs are set to prevent cache incoherent traffic, such as PCI no
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* snoop. This is set either at creation time or before the first map
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* operation.
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*/
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PT_FEAT_VTDSS_FORCE_COHERENCE = PT_FEAT_FMT_START,
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/*
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* Prevent creating read-only PTEs. Used to work around HW errata
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* ERRATA_772415_SPR17.
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*/
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PT_FEAT_VTDSS_FORCE_WRITEABLE,
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};
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struct pt_x86_64 {
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struct pt_common common;
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};
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@ -262,6 +262,17 @@ IOMMU_FORMAT(amdv1, amdpt);
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struct pt_iommu_amdv1_mock_hw_info;
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IOMMU_PROTOTYPES(amdv1_mock);
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struct pt_iommu_vtdss_cfg {
|
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struct pt_iommu_cfg common;
|
||||
};
|
||||
|
||||
struct pt_iommu_vtdss_hw_info {
|
||||
u64 ssptptr;
|
||||
u8 aw;
|
||||
};
|
||||
|
||||
IOMMU_FORMAT(vtdss, vtdss_pt);
|
||||
|
||||
struct pt_iommu_x86_64_cfg {
|
||||
struct pt_iommu_cfg common;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue