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x86/mce: Break up __mcheck_cpu_apply_quirks() 

Split each vendor specific part into its own helper function.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20241212140103.66964-5-qiuxu.zhuo@intel.com
This commit is contained in:
Tony Luck 2024-12-12 22:01:00 +08:00 committed by Borislav Petkov (AMD)
parent c46945c9ca
commit 51a12c28bb
1 changed files with 104 additions and 88 deletions
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60
arch/x86/kernel/cpu/mce/core.c
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@ -1910,19 +1910,11 @@ static void __mcheck_cpu_check_banks(void)
} }
} }
/* Add per CPU specific workarounds here */ static void apply_quirks_amd(struct cpuinfo_x86 *c)
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
{ {
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
struct mca_config *cfg = &mca_cfg;
if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
pr_info("unknown CPU type - not enabling MCE support\n");
return false;
}
/* This should be disabled by the BIOS, but isn't always */ /* This should be disabled by the BIOS, but isn't always */
if (c->x86_vendor == X86_VENDOR_AMD) {
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
/* /*
* disable GART TBL walk error reporting, which * disable GART TBL walk error reporting, which
@ -1931,13 +1923,15 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
*/ */
clear_bit(10, (unsigned long *)&mce_banks[4].ctl); clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
} }
if (c->x86 < 0x11 && cfg->bootlog < 0) {
if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
/* /*
* Lots of broken BIOS around that don't clear them * Lots of broken BIOS around that don't clear them
* by default and leave crap in there. Don't log: * by default and leave crap in there. Don't log:
*/ */
cfg->bootlog = 0; mca_cfg.bootlog = 0;
} }
/* /*
* Various K7s with broken bank 0 around. Always disable * Various K7s with broken bank 0 around. Always disable
* by default. * by default.
@ -1954,10 +1948,12 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
if (c->x86 >= 0x17 && c->x86 <= 0x1A) if (c->x86 >= 0x17 && c->x86 <= 0x1A)
mce_flags.zen_ifu_quirk = 1; mce_flags.zen_ifu_quirk = 1;
}
} static void apply_quirks_intel(struct cpuinfo_x86 *c)
{
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
if (c->x86_vendor == X86_VENDOR_INTEL) {
/* /*
* SDM documents that on family 6 bank 0 should not be written * SDM documents that on family 6 bank 0 should not be written
* because it aliases to another special BIOS controlled * because it aliases to another special BIOS controlled
@ -1966,7 +1962,6 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
* Don't ignore bank 0 completely because there could be a * Don't ignore bank 0 completely because there could be a
* valid event later, merely don't write CTL0. * valid event later, merely don't write CTL0.
*/ */
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
mce_banks[0].init = false; mce_banks[0].init = false;
@ -1975,15 +1970,15 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
* synchronization with a one second timeout. * synchronization with a one second timeout.
*/ */
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
cfg->monarch_timeout < 0) mca_cfg.monarch_timeout < 0)
cfg->monarch_timeout = USEC_PER_SEC; mca_cfg.monarch_timeout = USEC_PER_SEC;
/* /*
* There are also broken BIOSes on some Pentium M and * There are also broken BIOSes on some Pentium M and
* earlier systems: * earlier systems:
*/ */
if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0)
cfg->bootlog = 0; mca_cfg.bootlog = 0;
if (c->x86_vfm == INTEL_SANDYBRIDGE_X) if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
mce_flags.snb_ifu_quirk = 1; mce_flags.snb_ifu_quirk = 1;
@ -1994,17 +1989,38 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
*/ */
if (c->x86_vfm == INTEL_SKYLAKE_X) if (c->x86_vfm == INTEL_SKYLAKE_X)
mce_flags.skx_repmov_quirk = 1; mce_flags.skx_repmov_quirk = 1;
} }
if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
{
/* /*
* All newer Zhaoxin CPUs support MCE broadcasting. Enable * All newer Zhaoxin CPUs support MCE broadcasting. Enable
* synchronization with a one second timeout. * synchronization with a one second timeout.
*/ */
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
if (cfg->monarch_timeout < 0) if (mca_cfg.monarch_timeout < 0)
cfg->monarch_timeout = USEC_PER_SEC; mca_cfg.monarch_timeout = USEC_PER_SEC;
} }
}
/* Add per CPU specific workarounds here */
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
{
struct mca_config *cfg = &mca_cfg;
switch (c->x86_vendor) {
case X86_VENDOR_UNKNOWN:
pr_info("unknown CPU type - not enabling MCE support\n");
return false;
case X86_VENDOR_AMD:
apply_quirks_amd(c);
break;
case X86_VENDOR_INTEL:
apply_quirks_intel(c);
break;
case X86_VENDOR_ZHAOXIN:
apply_quirks_zhaoxin(c);
break;
} }
if (cfg->monarch_timeout < 0) if (cfg->monarch_timeout < 0)