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spi: aspeed: Use phys_addr_t for bus addresses to support 64-bit platforms 

Update bus address types from u32 to phys_addr_t to support systems with
64-bit memory address space. This change ensures compatibility with
upcoming SoCs that extend the system bus beyond 32-bit, while maintaining
support for existing platforms.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251114101042.1520997-4-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Chin-Ting Kuo 2025-11-14 18:10:41 +08:00 committed by Mark Brown
parent be6671d390
commit 508f3d3b68
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 17 additions and 15 deletions
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28
drivers/spi/spi-aspeed-smc.c
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@ -82,9 +82,10 @@ struct aspeed_spi_data {
u32 hdiv_max; u32 hdiv_max;
u32 min_window_size; u32 min_window_size;
u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg); phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg); phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg);
u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end); u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start,
phys_addr_t end);
int (*adjust_window)(struct aspeed_spi *aspi); int (*adjust_window)(struct aspeed_spi *aspi);
u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz); u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz);
int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv, int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
@ -97,7 +98,7 @@ struct aspeed_spi {
const struct aspeed_spi_data *data; const struct aspeed_spi_data *data;
void __iomem *regs; void __iomem *regs;
u32 ahb_base_phy; phys_addr_t ahb_base_phy;
u32 ahb_window_size; u32 ahb_window_size;
u32 num_cs; u32 num_cs;
struct device *dev; struct device *dev;
@ -484,9 +485,9 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi *aspi)
/* Assign the minimum window size to each CS */ /* Assign the minimum window size to each CS */
for (cs = 0; cs < aspi->num_cs; cs++) { for (cs = 0; cs < aspi->num_cs; cs++) {
aspi->chips[cs].ahb_window_size = aspi->data->min_window_size; aspi->chips[cs].ahb_window_size = aspi->data->min_window_size;
dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ]", dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]",
cs, aspi->ahb_base_phy + aspi->data->min_window_size * cs, cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs),
aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1); (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1));
} }
/* Close unused CS */ /* Close unused CS */
@ -930,17 +931,18 @@ static void aspeed_spi_remove(struct platform_device *pdev)
* The address range is encoded with absolute addresses in the overall * The address range is encoded with absolute addresses in the overall
* mapping window. * mapping window.
*/ */
static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
{ {
return ((reg >> 16) & 0xFF) << 23; return ((reg >> 16) & 0xFF) << 23;
} }
static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
{ {
return ((reg >> 24) & 0xFF) << 23; return ((reg >> 24) & 0xFF) << 23;
} }
static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end) static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi,
phys_addr_t start, phys_addr_t end)
{ {
return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
} }
@ -952,7 +954,7 @@ static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
#define AST2600_SEG_ADDR_MASK 0x0ff00000 #define AST2600_SEG_ADDR_MASK 0x0ff00000
static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
u32 reg) u32 reg)
{ {
u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
@ -960,7 +962,7 @@ static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
return aspi->ahb_base_phy + start_offset; return aspi->ahb_base_phy + start_offset;
} }
static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
u32 reg) u32 reg)
{ {
u32 end_offset = reg & AST2600_SEG_ADDR_MASK; u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
@ -973,7 +975,7 @@ static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
} }
static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
u32 start, u32 end) phys_addr_t start, phys_addr_t end)
{ {
/* disable zero size segments */ /* disable zero size segments */
if (start == end) if (start == end)