mirror of https://github.com/torvalds/linux.git
accel/amdxdna: Add error handling
When there is a hardware error, the NPU firmware notifies the host through a mailbox message. The message includes details of the error, such as the tile and column indexes where the error occurred. The driver starts a thread to handle the NPU error message. The thread stops the clients which are using the column where error occurred. Then the driver resets that column. Co-developed-by: Min Ma <min.ma@amd.com> Signed-off-by: Min Ma <min.ma@amd.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241118172942.2014541-10-lizhi.hou@amd.com
This commit is contained in:
Lizhi Hou
Jeffrey Hugo
parent
bed4c73e59
commit
4fd4ca984b
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@ -2,6 +2,7 @@
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amdxdna-y := \
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aie2_ctx.o \
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aie2_error.o \
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aie2_message.o \
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aie2_pci.o \
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aie2_psp.o \
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@ -0,0 +1,360 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/drm_cache.h>
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#include <drm/drm_device.h>
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#include <drm/drm_print.h>
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#include <drm/gpu_scheduler.h>
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#include <linux/dma-mapping.h>
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#include <linux/kthread.h>
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#include <linux/kernel.h>
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#include "aie2_msg_priv.h"
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#include "aie2_pci.h"
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#include "amdxdna_mailbox.h"
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#include "amdxdna_pci_drv.h"
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struct async_event {
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struct amdxdna_dev_hdl *ndev;
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struct async_event_msg_resp resp;
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struct workqueue_struct *wq;
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struct work_struct work;
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u8 *buf;
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dma_addr_t addr;
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u32 size;
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};
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struct async_events {
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struct workqueue_struct *wq;
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u8 *buf;
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dma_addr_t addr;
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u32 size;
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u32 event_cnt;
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struct async_event event[] __counted_by(event_cnt);
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};
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/*
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* Below enum, struct and lookup tables are porting from XAIE util header file.
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*
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* Below data is defined by AIE device and it is used for decode error message
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* from the device.
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*/
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enum aie_module_type {
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AIE_MEM_MOD = 0,
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AIE_CORE_MOD,
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AIE_PL_MOD,
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};
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enum aie_error_category {
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AIE_ERROR_SATURATION = 0,
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AIE_ERROR_FP,
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AIE_ERROR_STREAM,
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AIE_ERROR_ACCESS,
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AIE_ERROR_BUS,
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AIE_ERROR_INSTRUCTION,
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AIE_ERROR_ECC,
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AIE_ERROR_LOCK,
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AIE_ERROR_DMA,
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AIE_ERROR_MEM_PARITY,
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/* Unknown is not from XAIE, added for better category */
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AIE_ERROR_UNKNOWN,
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};
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/* Don't pack, unless XAIE side changed */
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struct aie_error {
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__u8 row;
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__u8 col;
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__u32 mod_type;
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__u8 event_id;
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};
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struct aie_err_info {
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u32 err_cnt;
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u32 ret_code;
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u32 rsvd;
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struct aie_error payload[] __counted_by(err_cnt);
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};
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struct aie_event_category {
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u8 event_id;
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enum aie_error_category category;
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};
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#define EVENT_CATEGORY(id, cat) { id, cat }
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static const struct aie_event_category aie_ml_mem_event_cat[] = {
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EVENT_CATEGORY(88U, AIE_ERROR_ECC),
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EVENT_CATEGORY(90U, AIE_ERROR_ECC),
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EVENT_CATEGORY(91U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(92U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(93U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(94U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(95U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(96U, AIE_ERROR_MEM_PARITY),
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EVENT_CATEGORY(97U, AIE_ERROR_DMA),
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EVENT_CATEGORY(98U, AIE_ERROR_DMA),
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EVENT_CATEGORY(99U, AIE_ERROR_DMA),
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EVENT_CATEGORY(100U, AIE_ERROR_DMA),
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EVENT_CATEGORY(101U, AIE_ERROR_LOCK),
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};
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static const struct aie_event_category aie_ml_core_event_cat[] = {
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EVENT_CATEGORY(55U, AIE_ERROR_ACCESS),
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EVENT_CATEGORY(56U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(57U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(58U, AIE_ERROR_BUS),
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EVENT_CATEGORY(59U, AIE_ERROR_INSTRUCTION),
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EVENT_CATEGORY(60U, AIE_ERROR_ACCESS),
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EVENT_CATEGORY(62U, AIE_ERROR_ECC),
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EVENT_CATEGORY(64U, AIE_ERROR_ECC),
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EVENT_CATEGORY(65U, AIE_ERROR_ACCESS),
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EVENT_CATEGORY(66U, AIE_ERROR_ACCESS),
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EVENT_CATEGORY(67U, AIE_ERROR_LOCK),
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EVENT_CATEGORY(70U, AIE_ERROR_INSTRUCTION),
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EVENT_CATEGORY(71U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(72U, AIE_ERROR_BUS),
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};
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static const struct aie_event_category aie_ml_mem_tile_event_cat[] = {
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EVENT_CATEGORY(130U, AIE_ERROR_ECC),
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EVENT_CATEGORY(132U, AIE_ERROR_ECC),
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EVENT_CATEGORY(133U, AIE_ERROR_DMA),
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EVENT_CATEGORY(134U, AIE_ERROR_DMA),
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EVENT_CATEGORY(135U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(136U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(137U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(138U, AIE_ERROR_BUS),
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EVENT_CATEGORY(139U, AIE_ERROR_LOCK),
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};
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static const struct aie_event_category aie_ml_shim_tile_event_cat[] = {
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EVENT_CATEGORY(64U, AIE_ERROR_BUS),
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EVENT_CATEGORY(65U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(66U, AIE_ERROR_STREAM),
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EVENT_CATEGORY(67U, AIE_ERROR_BUS),
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EVENT_CATEGORY(68U, AIE_ERROR_BUS),
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EVENT_CATEGORY(69U, AIE_ERROR_BUS),
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EVENT_CATEGORY(70U, AIE_ERROR_BUS),
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EVENT_CATEGORY(71U, AIE_ERROR_BUS),
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EVENT_CATEGORY(72U, AIE_ERROR_DMA),
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EVENT_CATEGORY(73U, AIE_ERROR_DMA),
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EVENT_CATEGORY(74U, AIE_ERROR_LOCK),
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};
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static enum aie_error_category
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aie_get_error_category(u8 row, u8 event_id, enum aie_module_type mod_type)
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{
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const struct aie_event_category *lut;
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int num_entry;
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int i;
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switch (mod_type) {
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case AIE_PL_MOD:
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lut = aie_ml_shim_tile_event_cat;
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num_entry = ARRAY_SIZE(aie_ml_shim_tile_event_cat);
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break;
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case AIE_CORE_MOD:
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lut = aie_ml_core_event_cat;
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num_entry = ARRAY_SIZE(aie_ml_core_event_cat);
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break;
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case AIE_MEM_MOD:
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if (row == 1) {
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lut = aie_ml_mem_tile_event_cat;
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num_entry = ARRAY_SIZE(aie_ml_mem_tile_event_cat);
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} else {
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lut = aie_ml_mem_event_cat;
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num_entry = ARRAY_SIZE(aie_ml_mem_event_cat);
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}
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break;
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default:
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return AIE_ERROR_UNKNOWN;
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}
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for (i = 0; i < num_entry; i++) {
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if (event_id != lut[i].event_id)
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continue;
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return lut[i].category;
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}
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return AIE_ERROR_UNKNOWN;
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}
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static u32 aie2_error_backtrack(struct amdxdna_dev_hdl *ndev, void *err_info, u32 num_err)
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{
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struct aie_error *errs = err_info;
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u32 err_col = 0; /* assume that AIE has less than 32 columns */
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int i;
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/* Get err column bitmap */
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for (i = 0; i < num_err; i++) {
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struct aie_error *err = &errs[i];
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enum aie_error_category cat;
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cat = aie_get_error_category(err->row, err->event_id, err->mod_type);
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XDNA_ERR(ndev->xdna, "Row: %d, Col: %d, module %d, event ID %d, category %d",
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err->row, err->col, err->mod_type,
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err->event_id, cat);
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if (err->col >= 32) {
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XDNA_WARN(ndev->xdna, "Invalid column number");
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break;
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}
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err_col |= (1 << err->col);
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}
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return err_col;
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}
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static int aie2_error_async_cb(void *handle, const u32 *data, size_t size)
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{
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struct async_event_msg_resp *resp;
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struct async_event *e = handle;
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if (data) {
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resp = (struct async_event_msg_resp *)data;
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e->resp.type = resp->type;
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wmb(); /* Update status in the end, so that no lock for here */
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e->resp.status = resp->status;
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}
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queue_work(e->wq, &e->work);
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return 0;
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}
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static int aie2_error_event_send(struct async_event *e)
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{
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drm_clflush_virt_range(e->buf, e->size); /* device can access */
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return aie2_register_asyn_event_msg(e->ndev, e->addr, e->size, e,
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aie2_error_async_cb);
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}
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static void aie2_error_worker(struct work_struct *err_work)
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{
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struct aie_err_info *info;
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struct amdxdna_dev *xdna;
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struct async_event *e;
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u32 max_err;
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u32 err_col;
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e = container_of(err_work, struct async_event, work);
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xdna = e->ndev->xdna;
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if (e->resp.status == MAX_AIE2_STATUS_CODE)
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return;
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e->resp.status = MAX_AIE2_STATUS_CODE;
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print_hex_dump_debug("AIE error: ", DUMP_PREFIX_OFFSET, 16, 4,
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e->buf, 0x100, false);
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info = (struct aie_err_info *)e->buf;
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XDNA_DBG(xdna, "Error count %d return code %d", info->err_cnt, info->ret_code);
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max_err = (e->size - sizeof(*info)) / sizeof(struct aie_error);
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if (unlikely(info->err_cnt > max_err)) {
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WARN_ONCE(1, "Error count too large %d\n", info->err_cnt);
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return;
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}
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err_col = aie2_error_backtrack(e->ndev, info->payload, info->err_cnt);
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if (!err_col) {
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XDNA_WARN(xdna, "Did not get error column");
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return;
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}
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mutex_lock(&xdna->dev_lock);
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/* Re-sent this event to firmware */
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if (aie2_error_event_send(e))
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XDNA_WARN(xdna, "Unable to register async event");
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mutex_unlock(&xdna->dev_lock);
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}
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int aie2_error_async_events_send(struct amdxdna_dev_hdl *ndev)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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struct async_event *e;
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int i, ret;
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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for (i = 0; i < ndev->async_events->event_cnt; i++) {
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e = &ndev->async_events->event[i];
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ret = aie2_error_event_send(e);
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if (ret)
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return ret;
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}
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return 0;
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}
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void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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struct async_events *events;
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events = ndev->async_events;
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mutex_unlock(&xdna->dev_lock);
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destroy_workqueue(events->wq);
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mutex_lock(&xdna->dev_lock);
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dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf,
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events->addr, DMA_FROM_DEVICE);
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kfree(events);
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}
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int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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u32 total_col = ndev->total_col;
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u32 total_size = ASYNC_BUF_SIZE * total_col;
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struct async_events *events;
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int i, ret;
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events = kzalloc(struct_size(events, event, total_col), GFP_KERNEL);
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if (!events)
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return -ENOMEM;
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events->buf = dma_alloc_noncoherent(xdna->ddev.dev, total_size, &events->addr,
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DMA_FROM_DEVICE, GFP_KERNEL);
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if (!events->buf) {
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ret = -ENOMEM;
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goto free_events;
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}
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events->size = total_size;
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events->event_cnt = total_col;
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events->wq = alloc_ordered_workqueue("async_wq", 0);
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if (!events->wq) {
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ret = -ENOMEM;
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goto free_buf;
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}
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for (i = 0; i < events->event_cnt; i++) {
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struct async_event *e = &events->event[i];
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u32 offset = i * ASYNC_BUF_SIZE;
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e->ndev = ndev;
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e->wq = events->wq;
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e->buf = &events->buf[offset];
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e->addr = events->addr + offset;
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e->size = ASYNC_BUF_SIZE;
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e->resp.status = MAX_AIE2_STATUS_CODE;
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INIT_WORK(&e->work, aie2_error_worker);
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}
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ndev->async_events = events;
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XDNA_DBG(xdna, "Async event count %d, buf total size 0x%x",
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events->event_cnt, events->size);
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return 0;
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free_buf:
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dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf,
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events->addr, DMA_FROM_DEVICE);
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free_events:
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kfree(events);
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return ret;
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}
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@ -308,6 +308,25 @@ int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u6
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return 0;
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}
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int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size,
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void *handle, int (*cb)(void*, const u32 *, size_t))
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{
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struct async_event_msg_req req = { 0 };
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struct xdna_mailbox_msg msg = {
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.send_data = (u8 *)&req,
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.send_size = sizeof(req),
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.handle = handle,
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.opcode = MSG_OP_REGISTER_ASYNC_EVENT_MSG,
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.notify_cb = cb,
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};
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req.buf_addr = addr;
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req.buf_size = size;
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XDNA_DBG(ndev->xdna, "Register addr 0x%llx size 0x%x", addr, size);
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return xdna_mailbox_send_msg(ndev->mgmt_chann, &msg, TX_TIMEOUT);
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}
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int aie2_config_cu(struct amdxdna_hwctx *hwctx)
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{
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struct mailbox_channel *chann = hwctx->priv->mbox_chann;
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@ -180,6 +180,15 @@ static int aie2_mgmt_fw_init(struct amdxdna_dev_hdl *ndev)
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return ret;
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}
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if (!ndev->async_events)
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return 0;
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ret = aie2_error_async_events_send(ndev);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Send async events failed");
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return ret;
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}
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return 0;
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}
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@ -469,9 +478,30 @@ static int aie2_init(struct amdxdna_dev *xdna)
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goto stop_hw;
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}
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ret = aie2_error_async_events_alloc(ndev);
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if (ret) {
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XDNA_ERR(xdna, "Allocate async events failed, ret %d", ret);
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goto stop_hw;
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}
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ret = aie2_error_async_events_send(ndev);
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if (ret) {
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XDNA_ERR(xdna, "Send async events failed, ret %d", ret);
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goto async_event_free;
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}
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/* Issue a command to make sure firmware handled async events */
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ret = aie2_query_firmware_version(ndev, &ndev->xdna->fw_ver);
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if (ret) {
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XDNA_ERR(xdna, "Re-query firmware version failed");
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goto async_event_free;
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}
|
||||
|
||||
release_firmware(fw);
|
||||
return 0;
|
||||
|
||||
async_event_free:
|
||||
aie2_error_async_events_free(ndev);
|
||||
stop_hw:
|
||||
aie2_hw_stop(xdna);
|
||||
disable_sva:
|
||||
|
|
@ -487,8 +517,10 @@ static int aie2_init(struct amdxdna_dev *xdna)
|
|||
static void aie2_fini(struct amdxdna_dev *xdna)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
|
||||
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
|
||||
|
||||
aie2_hw_stop(xdna);
|
||||
aie2_error_async_events_free(ndev);
|
||||
iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
|
||||
pci_free_irq_vectors(pdev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -170,6 +170,7 @@ struct amdxdna_dev_hdl {
|
|||
/* Mailbox and the management channel */
|
||||
struct mailbox *mbox;
|
||||
struct mailbox_channel *mgmt_chann;
|
||||
struct async_events *async_events;
|
||||
};
|
||||
|
||||
#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \
|
||||
|
|
@ -210,6 +211,12 @@ struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *
|
|||
int aie2_psp_start(struct psp_device *psp);
|
||||
void aie2_psp_stop(struct psp_device *psp);
|
||||
|
||||
/* aie2_error.c */
|
||||
int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev);
|
||||
void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev);
|
||||
int aie2_error_async_events_send(struct amdxdna_dev_hdl *ndev);
|
||||
int aie2_error_async_msg_thread(void *data);
|
||||
|
||||
/* aie2_message.c */
|
||||
int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
|
||||
int aie2_resume_fw(struct amdxdna_dev_hdl *ndev);
|
||||
|
|
@ -224,6 +231,8 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
|
|||
int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
|
||||
int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
|
||||
int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size);
|
||||
int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size,
|
||||
void *handle, int (*cb)(void*, const u32 *, size_t));
|
||||
int aie2_config_cu(struct amdxdna_hwctx *hwctx);
|
||||
int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
|
||||
int (*notify_cb)(void *, const u32 *, size_t));
|
||||
|
|
|
|||
Loading…
Reference in New Issue