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drm/i915: Reoder BDW+ EU/slice fuse bits 

We customarily define the bits of a register in big endian
order. Reorder the BDW+ fuse bits to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-11-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2025-02-12 01:19:38 +02:00 committed by Andi Shyti
parent d75131164e
commit 4cdaba1bb0
1 changed files with 16 additions and 15 deletions
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31
drivers/gpu/drm/i915/gt/intel_gt_regs.h
View File

@ -515,10 +515,11 @@
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
((slice) % 3) * 0x4)
#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
@ -527,14 +528,14 @@
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
((slice) % 3) * 0x8)
#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
#define VF_PREEMPTION _MMIO(0x83a4)
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
@ -601,24 +602,24 @@
#define HSW_F1_EU_DIS_6EUS 2
#define GEN8_FUSE2 _MMIO(0x9120)
#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
#define GEN11_EU_DISABLE _MMIO(0x9134)
#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
#define XEHP_EU_ENABLE _MMIO(0x9134)
#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
#define GEN8_EU_DISABLE1 _MMIO(0x9138)
#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
@ -632,8 +633,8 @@
#define GEN10_EU_DISABLE3 _MMIO(0x9140)
#define GEN10_EU_DIS_SS_MASK 0xff
#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)