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power: supply: qcom_battmgr: support disabling charge control 

Existing userspace (in particular, upower) disables charge control by
setting the start threshold to 0 and the stop threshold to 100.

Handle that by actually setting the enable bit to 0 when a start
threshold of 0 was requested.

Fixes: cc3e883a06 ("power: supply: qcom_battmgr: Add charge control support")
Signed-off-by: Val Packett <val@packett.cool>
Link: https://patch.msgid.link/20251012233333.19144-4-val@packett.cool
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
This commit is contained in:
Val Packett 2025-10-12 20:32:19 -03:00 committed by Sebastian Reichel
parent 8809980fdc
commit 446fcf4946
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/power/supply/qcom_battmgr.c
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@ -257,6 +257,7 @@ struct qcom_battmgr_info {
unsigned int capacity_warning;
unsigned int cycle_count;
unsigned int charge_count;
bool charge_ctrl_enable;
unsigned int charge_ctrl_start;
unsigned int charge_ctrl_end;
char model_number[BATTMGR_STRING_LEN];
@ -659,13 +660,13 @@ static int qcom_battmgr_bat_get_property(struct power_supply *psy,
}
static int qcom_battmgr_set_charge_control(struct qcom_battmgr *battmgr,
u32 target_soc, u32 delta_soc)
bool enable, u32 target_soc, u32 delta_soc)
{
struct qcom_battmgr_charge_ctrl_request request = {
.hdr.owner = cpu_to_le32(PMIC_GLINK_OWNER_BATTMGR),
.hdr.type = cpu_to_le32(PMIC_GLINK_REQ_RESP),
.hdr.opcode = cpu_to_le32(BATTMGR_CHG_CTRL_LIMIT_EN),
.enable = cpu_to_le32(1),
.enable = cpu_to_le32(enable),
.target_soc = cpu_to_le32(target_soc),
.delta_soc = cpu_to_le32(delta_soc),
};
@ -677,6 +678,7 @@ static int qcom_battmgr_set_charge_start_threshold(struct qcom_battmgr *battmgr,
{
u32 target_soc, delta_soc;
int ret;
bool enable = start_soc != 0;
start_soc = clamp(start_soc, CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_START_THR_MAX);
@ -696,9 +698,10 @@ static int qcom_battmgr_set_charge_start_threshold(struct qcom_battmgr *battmgr,
}
mutex_lock(&battmgr->lock);
ret = qcom_battmgr_set_charge_control(battmgr, target_soc, delta_soc);
ret = qcom_battmgr_set_charge_control(battmgr, enable, target_soc, delta_soc);
mutex_unlock(&battmgr->lock);
if (!ret) {
battmgr->info.charge_ctrl_enable = enable;
battmgr->info.charge_ctrl_start = start_soc;
battmgr->info.charge_ctrl_end = target_soc;
}
@ -710,6 +713,7 @@ static int qcom_battmgr_set_charge_end_threshold(struct qcom_battmgr *battmgr, i
{
u32 delta_soc = CHARGE_CTRL_DELTA_SOC;
int ret;
bool enable = battmgr->info.charge_ctrl_enable;
end_soc = clamp(end_soc, CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_MAX);
@ -717,7 +721,7 @@ static int qcom_battmgr_set_charge_end_threshold(struct qcom_battmgr *battmgr, i
delta_soc = end_soc - battmgr->info.charge_ctrl_start;
mutex_lock(&battmgr->lock);
ret = qcom_battmgr_set_charge_control(battmgr, end_soc, delta_soc);
ret = qcom_battmgr_set_charge_control(battmgr, enable, end_soc, delta_soc);
mutex_unlock(&battmgr->lock);
if (!ret) {
battmgr->info.charge_ctrl_start = end_soc - delta_soc;