mirror of https://github.com/torvalds/linux.git
pwm: stm32-lp: Add support for stm32mp25
Add support for STM32MP25 SoC. A new compatible has been added to the dt-bindings. It represents handle new features, registers and bits diversity. It isn't used currently in the driver, as matching is done by retrieving MFD parent data. New dedicated capture/compare channels has been added: e.g. a new compare register for channel 2. Some controls (polarity / cc channel enable) are handled in CCMR register on this new variant (instead of wavepol bit). So, Low-power timer can now have up to two PWM outputs. Use device data from the MFD parent to configure the number of PWM channels e.g. 'npwm'. Update current get_state() and apply() ops to support either: - one PWM channel (as on older revision, or LPTIM5 on STM32MP25) - two PWM channels (e.g. LPTIM1/2/3/4 on STM32MP25 that has the full feature set) Introduce new routines to manage common prescaler, reload register and global enable bit. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> Link: https://lore.kernel.org/r/20250429125133.1574167-5-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Fabrice Gasnier
Lee Jones
parent
5414bc8c57
commit
3f51b232c1
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@ -20,6 +20,7 @@
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struct stm32_pwm_lp {
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struct clk *clk;
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struct regmap *regmap;
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unsigned int num_cc_chans;
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};
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static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
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@ -30,13 +31,101 @@ static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
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/* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
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#define STM32_LPTIM_MAX_PRESCALER 128
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static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int channel)
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{
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int ret;
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u32 ccmr1;
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unsigned long ccmr;
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/* Only one PWM on this LPTIMER: enable, prescaler and reload value can be changed */
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if (!priv->num_cc_chans)
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return true;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1);
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if (ret)
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return ret;
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ccmr = ccmr1 & (STM32_LPTIM_CC1E | STM32_LPTIM_CC2E);
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/* More than one channel enabled: enable, prescaler or ARR value can't be changed */
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if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1)
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return false;
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/*
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* Only one channel is enabled (or none): check status on the other channel, to
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* report if enable, prescaler or ARR value can be changed.
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*/
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if (channel)
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return !(ccmr1 & STM32_LPTIM_CC1E);
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else
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return !(ccmr1 & STM32_LPTIM_CC2E);
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}
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static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, int channel,
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bool enable, enum pwm_polarity polarity)
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{
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u32 ccmr1, val, mask;
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bool reenable;
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int ret;
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/* No dedicated CC channel: nothing to do */
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if (!priv->num_cc_chans)
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return 0;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1);
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if (ret)
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return ret;
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if (channel) {
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/* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-enable */
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reenable = (enable && FIELD_GET(STM32_LPTIM_CC2E, ccmr1)) &&
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(polarity != FIELD_GET(STM32_LPTIM_CC2P, ccmr1));
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mask = STM32_LPTIM_CC2SEL | STM32_LPTIM_CC2E | STM32_LPTIM_CC2P;
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val = FIELD_PREP(STM32_LPTIM_CC2P, polarity);
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val |= FIELD_PREP(STM32_LPTIM_CC2E, enable);
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} else {
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reenable = (enable && FIELD_GET(STM32_LPTIM_CC1E, ccmr1)) &&
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(polarity != FIELD_GET(STM32_LPTIM_CC1P, ccmr1));
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mask = STM32_LPTIM_CC1SEL | STM32_LPTIM_CC1E | STM32_LPTIM_CC1P;
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val = FIELD_PREP(STM32_LPTIM_CC1P, polarity);
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val |= FIELD_PREP(STM32_LPTIM_CC1E, enable);
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}
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if (reenable) {
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u32 cfgr, presc;
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unsigned long rate;
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unsigned int delay_us;
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ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1,
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channel ? STM32_LPTIM_CC2E : STM32_LPTIM_CC1E, 0);
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if (ret)
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return ret;
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/*
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* After a write to the LPTIM_CCMRx register, a new write operation can only be
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* performed after a delay of at least (PRESC × 3) clock cycles
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*/
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ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
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if (ret)
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return ret;
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presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr);
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rate = clk_get_rate(priv->clk) >> presc;
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if (!rate)
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return -EINVAL;
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delay_us = 3 * DIV_ROUND_UP(USEC_PER_SEC, rate);
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usleep_range(delay_us, delay_us * 2);
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}
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return regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, mask, val);
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}
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static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
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unsigned long long prd, div, dty;
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struct pwm_state cstate;
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u32 val, mask, cfgr, presc = 0;
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u32 arr, val, mask, cfgr, presc = 0;
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bool reenable;
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int ret;
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@ -45,10 +134,28 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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if (!state->enabled) {
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if (cstate.enabled) {
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/* Disable CC channel if any */
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ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false,
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state->polarity);
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if (ret)
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return ret;
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ret = regmap_write(priv->regmap, pwm->hwpwm ?
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STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 0);
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if (ret)
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return ret;
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/* Check if the timer can be disabled */
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ret = stm32_pwm_lp_update_allowed(priv, pwm->hwpwm);
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if (ret < 0)
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return ret;
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if (ret) {
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/* Disable LP timer */
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
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if (ret)
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return ret;
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}
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/* disable clock to PWM counter */
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clk_disable(priv->clk);
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}
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@ -79,6 +186,23 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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dty = prd * state->duty_cycle;
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do_div(dty, state->period);
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ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
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if (ret)
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return ret;
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/*
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* When there are several channels, they share the same prescaler and reload value.
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* Check if this can be changed, or the values are the same for all channels.
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*/
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if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) {
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ret = regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr);
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if (ret)
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return ret;
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if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1))
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return -EBUSY;
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}
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if (!cstate.enabled) {
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/* enable clock to drive PWM counter */
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ret = clk_enable(priv->clk);
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@ -86,15 +210,20 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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return ret;
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}
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ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
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if (ret)
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goto err;
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if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
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(FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
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((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) {
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val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
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mask = STM32_LPTIM_PRESC;
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if (!priv->num_cc_chans) {
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/*
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* WAVPOL bit is only available when no capature compare channel is used,
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* e.g. on LPTIMER instances that have only one output channel. CCMR1 is
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* used otherwise.
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*/
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val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
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mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
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mask |= STM32_LPTIM_WAVPOL;
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}
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/* Must disable LP timer to modify CFGR */
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reenable = true;
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@ -120,20 +249,27 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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if (ret)
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goto err;
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ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
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/* Write CMP/CCRx register and ensure it's been properly written */
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ret = regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP,
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prd - (1 + dty));
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if (ret)
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goto err;
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/* ensure CMP & ARR registers are properly written */
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ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
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/* ensure ARR and CMP/CCRx registers are properly written */
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ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm->hwpwm ?
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(val & STM32_LPTIM_CMP2_ARROK) == STM32_LPTIM_CMP2_ARROK :
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(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
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100, 1000);
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if (ret) {
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dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n");
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goto err;
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}
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ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
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STM32_LPTIM_CMPOKCF_ARROKCF);
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ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ?
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STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF);
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if (ret)
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goto err;
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ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state->polarity);
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if (ret)
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goto err;
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@ -161,11 +297,22 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *chip,
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{
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struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
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unsigned long rate = clk_get_rate(priv->clk);
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u32 val, presc, prd;
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u32 val, presc, prd, ccmr1;
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bool enabled;
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u64 tmp;
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regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
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state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
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enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
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if (priv->num_cc_chans) {
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/* There's a CC chan, need to also check if it's enabled */
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regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1);
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if (pwm->hwpwm)
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enabled &= !!FIELD_GET(STM32_LPTIM_CC2E, ccmr1);
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else
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enabled &= !!FIELD_GET(STM32_LPTIM_CC1E, ccmr1);
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}
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state->enabled = enabled;
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/* Keep PWM counter clock refcount in sync with PWM initial state */
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if (state->enabled) {
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int ret = clk_enable(priv->clk);
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@ -176,14 +323,21 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *chip,
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regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
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presc = FIELD_GET(STM32_LPTIM_PRESC, val);
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if (priv->num_cc_chans) {
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if (pwm->hwpwm)
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state->polarity = FIELD_GET(STM32_LPTIM_CC2P, ccmr1);
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else
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state->polarity = FIELD_GET(STM32_LPTIM_CC1P, ccmr1);
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} else {
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state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val);
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}
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regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd);
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tmp = prd + 1;
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tmp = (tmp << presc) * NSEC_PER_SEC;
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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regmap_read(priv->regmap, STM32_LPTIM_CMP, &val);
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regmap_read(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, &val);
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tmp = prd - val;
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tmp = (tmp << presc) * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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@ -201,15 +355,25 @@ static int stm32_pwm_lp_probe(struct platform_device *pdev)
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struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
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struct stm32_pwm_lp *priv;
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struct pwm_chip *chip;
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unsigned int npwm;
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int ret;
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chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv));
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if (!ddata->num_cc_chans) {
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/* No dedicated CC channel, so there's only one PWM channel */
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npwm = 1;
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} else {
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/* There are dedicated CC channels, each with one PWM output */
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npwm = ddata->num_cc_chans;
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}
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chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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priv = to_stm32_pwm_lp(chip);
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->num_cc_chans = ddata->num_cc_chans;
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chip->ops = &stm32_pwm_lp_ops;
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ret = devm_pwmchip_add(&pdev->dev, chip);
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@ -225,13 +389,16 @@ static int stm32_pwm_lp_suspend(struct device *dev)
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{
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struct pwm_chip *chip = dev_get_drvdata(dev);
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struct pwm_state state;
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unsigned int i;
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pwm_get_state(&chip->pwms[0], &state);
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for (i = 0; i < chip->npwm; i++) {
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pwm_get_state(&chip->pwms[i], &state);
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if (state.enabled) {
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dev_err(dev, "The consumer didn't stop us (%s)\n",
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chip->pwms[0].label);
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chip->pwms[i].label);
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return -EBUSY;
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}
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}
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return pinctrl_pm_select_sleep_state(dev);
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}
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