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Allwinner fixes for 6.18 

Just one fix to correct the "thead,vlenb" property for the RISC-V based
 D1 SoC family.
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Merge tag 'sunxi-fixes-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes

Allwinner fixes for 6.18

Just one fix to correct the "thead,vlenb" property for the RISC-V based
D1 SoC family.

* tag 'sunxi-fixes-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  riscv: dts: allwinner: d1: fix vlenb property
This commit is contained in:
Arnd Bergmann 2025-11-28 17:37:13 +01:00
parent a6737fe620 9f393d8e75
commit 3ecfcf34f0
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
View File

@ -28,7 +28,7 @@ cpu0: cpu@0 {
riscv,isa-base = "rv64i"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector"; "zifencei", "zihpm", "xtheadvector";
thead,vlenb = <128>; thead,vlenb = <16>;
#cooling-cells = <2>; #cooling-cells = <2>;
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {