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pmdomain: Merge branch dt into next 

Merge the immutable branch dt into next, to allow the DT bindings to be
tested together with changes that are targeted for v6.19.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ulf Hansson 2025-11-19 18:03:56 +01:00
parent 6a23ae0a96 34194cb385
commit 35cfef3ccb
8 changed files with 234 additions and 6 deletions
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117
Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml Normal file
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@ -0,0 +1,117 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MFlexGraphics Power and Frequency Controller
maintainers:
- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
description:
A special-purpose embedded MCU to control power and frequency of GPU devices
using MediaTek Flexible Graphics integration hardware.
properties:
$nodename:
pattern: '^power-controller@[a-f0-9]+$'
compatible:
enum:
- mediatek,mt8196-gpufreq
reg:
items:
- description: GPR memory area
- description: RPC memory area
- description: SoC variant ID register
reg-names:
items:
- const: gpr
- const: rpc
- const: hw-revision
clocks:
items:
- description: main clock of the embedded controller (EB)
- description: core PLL
- description: stack 0 PLL
- description: stack 1 PLL
clock-names:
items:
- const: eb
- const: core
- const: stack0
- const: stack1
mboxes:
items:
- description: FastDVFS events
- description: frequency control
- description: sleep control
- description: timer control
- description: frequency hopping control
- description: hardware voter control
- description: FastDVFS control
mbox-names:
items:
- const: fast-dvfs-event
- const: gpufreq
- const: sleep
- const: timer
- const: fhctl
- const: ccf
- const: fast-dvfs
memory-region:
items:
- description: phandle to the GPUEB shared memory
"#clock-cells":
const: 1
"#power-domain-cells":
const: 0
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- mboxes
- mbox-names
- memory-region
- "#clock-cells"
- "#power-domain-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
power-controller@4b09fd00 {
compatible = "mediatek,mt8196-gpufreq";
reg = <0x4b09fd00 0x80>,
<0x4b800000 0x1000>,
<0x4b860128 0x4>;
reg-names = "gpr", "rpc", "hw-revision";
clocks = <&topckgen CLK_TOP_MFG_EB>,
<&mfgpll CLK_MFG_AO_MFGPLL>,
<&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
<&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
clock-names = "eb", "core", "stack0", "stack1";
mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
<&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
<&gpueb_mbox 7>;
mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
"ccf", "fast-dvfs";
memory-region = <&gpueb_shared_memory>;
#clock-cells = <1>;
#power-domain-cells = <0>;
};

4
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
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@ -33,6 +33,9 @@ properties:
- mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
- mediatek,mt8196-hwv-hfrp-power-controller
- mediatek,mt8196-hwv-scp-power-controller
- mediatek,mt8196-power-controller
- mediatek,mt8365-power-controller
'#power-domain-cells':
@ -157,6 +160,7 @@ allOf:
contains:
enum:
- mediatek,mt8183-power-controller
- mediatek,mt8196-power-controller
then:
properties:
access-controllers:

1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
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@ -18,6 +18,7 @@ properties:
oneOf:
- enum:
- qcom,glymur-rpmhpd
- qcom,kaanapali-rpmhpd
- qcom,mdm9607-rpmpd
- qcom,milos-rpmhpd
- qcom,msm8226-rpmpd

2
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
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@ -46,6 +46,7 @@ properties:
- rockchip,rk3576-power-controller
- rockchip,rk3588-power-controller
- rockchip,rv1126-power-controller
- rockchip,rv1126b-power-controller
"#power-domain-cells":
const: 1
@ -126,6 +127,7 @@ $defs:
"include/dt-bindings/power/rk3568-power.h"
"include/dt-bindings/power/rk3588-power.h"
"include/dt-bindings/power/rockchip,rv1126-power.h"
"include/dt-bindings/power/rockchip,rv1126b-power-controller.h"
clocks:
minItems: 1

38
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml
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@ -13,23 +13,21 @@ description: |
maintainers:
- Nicolas Saenz Julienne <nsaenz@kernel.org>
allOf:
- $ref: /schemas/watchdog/watchdog.yaml#
properties:
compatible:
items:
- enum:
- brcm,bcm2835-pm
- brcm,bcm2711-pm
- brcm,bcm2712-pm
- const: brcm,bcm2835-pm-wdt
reg:
minItems: 2
minItems: 1
maxItems: 3
reg-names:
minItems: 2
minItems: 1
items:
- const: pm
- const: asb
@ -62,7 +60,35 @@ required:
- reg
- "#power-domain-cells"
- "#reset-cells"
- clocks
allOf:
- $ref: /schemas/watchdog/watchdog.yaml#
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm2835-pm
- brcm,bcm2711-pm
then:
required:
- clocks
properties:
reg:
minItems: 2
reg-names:
minItems: 2
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
additionalProperties: false

58
include/dt-bindings/power/mediatek,mt8196-power.h Normal file
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@ -0,0 +1,58 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2025 Collabora Ltd
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H
#define _DT_BINDINGS_POWER_MT8196_POWER_H
/* SCPSYS Secure Power Manager - Direct Control */
#define MT8196_POWER_DOMAIN_MD 0
#define MT8196_POWER_DOMAIN_CONN 1
#define MT8196_POWER_DOMAIN_SSUSB_P0 2
#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 3
#define MT8196_POWER_DOMAIN_SSUSB_P1 4
#define MT8196_POWER_DOMAIN_SSUSB_P23 5
#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 6
#define MT8196_POWER_DOMAIN_PEXTP_MAC0 7
#define MT8196_POWER_DOMAIN_PEXTP_MAC1 8
#define MT8196_POWER_DOMAIN_PEXTP_MAC2 9
#define MT8196_POWER_DOMAIN_PEXTP_PHY0 10
#define MT8196_POWER_DOMAIN_PEXTP_PHY1 11
#define MT8196_POWER_DOMAIN_PEXTP_PHY2 12
#define MT8196_POWER_DOMAIN_AUDIO 13
#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 14
#define MT8196_POWER_DOMAIN_ADSP_INFRA 15
#define MT8196_POWER_DOMAIN_ADSP_AO 16
/* SCPSYS Secure Power Manager - HW Voter */
#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 0
#define MT8196_POWER_DOMAIN_SSR 1
/* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */
#define MT8196_POWER_DOMAIN_VDE0 0
#define MT8196_POWER_DOMAIN_VDE1 1
#define MT8196_POWER_DOMAIN_VDE_VCORE0 2
#define MT8196_POWER_DOMAIN_VEN0 3
#define MT8196_POWER_DOMAIN_VEN1 4
#define MT8196_POWER_DOMAIN_VEN2 5
#define MT8196_POWER_DOMAIN_DISP_VCORE 6
#define MT8196_POWER_DOMAIN_DIS0_DORMANT 7
#define MT8196_POWER_DOMAIN_DIS1_DORMANT 8
#define MT8196_POWER_DOMAIN_OVL0_DORMANT 9
#define MT8196_POWER_DOMAIN_OVL1_DORMANT 10
#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 11
#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 12
#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 13
#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 14
#define MT8196_POWER_DOMAIN_MM_INFRA0 15
#define MT8196_POWER_DOMAIN_MM_INFRA1 16
#define MT8196_POWER_DOMAIN_MM_INFRA_AO 17
#define MT8196_POWER_DOMAIN_CSI_BS_RX 18
#define MT8196_POWER_DOMAIN_CSI_LS_RX 19
#define MT8196_POWER_DOMAIN_DSI_PHY0 20
#define MT8196_POWER_DOMAIN_DSI_PHY1 21
#define MT8196_POWER_DOMAIN_DSI_PHY2 22
#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */

3
include/dt-bindings/power/qcom,rpmhpd.h
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@ -33,11 +33,14 @@
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L0 76
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
#define RPMH_REGULATOR_LEVEL_SVS 128

17
include/dt-bindings/power/rockchip,rv1126b-power-controller.h Normal file
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@ -0,0 +1,17 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
#define __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
/* VD_NPU */
#define RV1126B_PD_NPU 0
/* VD_LOGIC */
#define RV1126B_PD_VDO 1
#define RV1126B_PD_AIISP 2
#endif