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spi: cadence-quadspi: Support for device reset via OSPI controller 

Add support for flash device reset via ospi controller, instead of
using GPIO, as ospi IP has device reset feature on Versal Gen2 platform.

Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Link: https://patch.msgid.link/20241120120951.56327-4-srikanth.boyapally@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srikanth Boyapally 2024-11-20 17:39:51 +05:30 committed by Mark Brown
parent 2e4d9f5111
commit 27cf57f65b
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 39 additions and 1 deletions
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40
drivers/spi/spi-cadence-quadspi.c
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@ -44,6 +44,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
#define CQSPI_RD_NO_IRQ BIT(6) #define CQSPI_RD_NO_IRQ BIT(6)
#define CQSPI_DMA_SET_MASK BIT(7) #define CQSPI_DMA_SET_MASK BIT(7)
#define CQSPI_SUPPORT_DEVICE_RESET BIT(8)
/* Capabilities */ /* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0) #define CQSPI_SUPPORTS_OCTAL BIT(0)
@ -110,7 +111,7 @@ struct cqspi_st {
struct cqspi_driver_platdata { struct cqspi_driver_platdata {
u32 hwcaps_mask; u32 hwcaps_mask;
u8 quirks; u16 quirks;
int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
u_char *rxbuf, loff_t from_addr, size_t n_rx); u_char *rxbuf, loff_t from_addr, size_t n_rx);
u32 (*get_dma_status)(struct cqspi_st *cqspi); u32 (*get_dma_status)(struct cqspi_st *cqspi);
@ -145,6 +146,8 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_CONFIG_IDLE_LSB 31 #define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5)
#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6)
#define CQSPI_REG_RD_INSTR 0x04 #define CQSPI_REG_RD_INSTR 0x04
#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
@ -831,6 +834,25 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
return ret; return ret;
} }
static void cqspi_device_reset(struct cqspi_st *cqspi)
{
u32 reg;
reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
/*
* NOTE: Delay timing implementation is derived from
* spi_nor_hw_reset()
*/
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
usleep_range(1, 5);
writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
usleep_range(100, 150);
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
usleep_range(1000, 1200);
}
static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
{ {
void __iomem *reg_base = cqspi->iobase; void __iomem *reg_base = cqspi->iobase;
@ -1912,6 +1934,9 @@ static int cqspi_probe(struct platform_device *pdev)
host->num_chipselect = cqspi->num_chipselect; host->num_chipselect = cqspi->num_chipselect;
if (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)
cqspi_device_reset(cqspi);
if (cqspi->use_direct_mode) { if (cqspi->use_direct_mode) {
ret = cqspi_request_mmap_dma(cqspi); ret = cqspi_request_mmap_dma(cqspi);
if (ret == -EPROBE_DEFER) if (ret == -EPROBE_DEFER)
@ -2054,6 +2079,15 @@ static const struct cqspi_driver_platdata versal_ospi = {
.get_dma_status = cqspi_get_versal_dma_status, .get_dma_status = cqspi_get_versal_dma_status,
}; };
static const struct cqspi_driver_platdata versal2_ospi = {
.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA
| CQSPI_DMA_SET_MASK
| CQSPI_SUPPORT_DEVICE_RESET,
.indirect_read_dma = cqspi_versal_indirect_read_dma,
.get_dma_status = cqspi_get_versal_dma_status,
};
static const struct cqspi_driver_platdata jh7110_qspi = { static const struct cqspi_driver_platdata jh7110_qspi = {
.quirks = CQSPI_DISABLE_DAC_MODE, .quirks = CQSPI_DISABLE_DAC_MODE,
.jh7110_clk_init = cqspi_jh7110_clk_init, .jh7110_clk_init = cqspi_jh7110_clk_init,
@ -2106,6 +2140,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "mobileye,eyeq5-ospi", .compatible = "mobileye,eyeq5-ospi",
.data = &mobileye_eyeq5_ospi, .data = &mobileye_eyeq5_ospi,
}, },
{
.compatible = "amd,versal2-ospi",
.data = &versal2_ospi,
},
{ /* end of table */ } { /* end of table */ }
}; };