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dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
Convert nxp,lpc1850-rgu.txt to yaml format. Additional changes: - remove label in example. - remove reset consumer in example. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250602144046.943982-1-Frank.Li@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Frank Li
Philipp Zabel
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e73bfb4ca5
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25ef956349
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NXP LPC1850 Reset Generation Unit (RGU)
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========================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "nxp,lpc1850-rgu"
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- reg: register base and length
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- clocks: phandle and clock specifier to RGU clocks
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- clock-names: should contain "delay" and "reg"
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- #reset-cells: should be 1
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See table below for valid peripheral reset numbers. Numbers not
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in the table below are either reserved or not applicable for
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normal operation.
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Reset Peripheral
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9 System control unit (SCU)
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12 ARM Cortex-M0 subsystem core (LPC43xx only)
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13 CPU core
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16 LCD controller
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17 USB0
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18 USB1
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19 DMA
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20 SDIO
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21 External memory controller (EMC)
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22 Ethernet
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25 Flash bank A
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27 EEPROM
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28 GPIO
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29 Flash bank B
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32 Timer0
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33 Timer1
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34 Timer2
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35 Timer3
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36 Repetitive Interrupt timer (RIT)
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37 State Configurable Timer (SCT)
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38 Motor control PWM (MCPWM)
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39 QEI
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40 ADC0
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41 ADC1
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42 DAC
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44 USART0
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45 UART1
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46 USART2
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47 USART3
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48 I2C0
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49 I2C1
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50 SSP0
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51 SSP1
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52 I2S0 and I2S1
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53 Serial Flash Interface (SPIFI)
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54 C_CAN1
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55 C_CAN0
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56 ARM Cortex-M0 application core (LPC4370 only)
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57 SGPIO (LPC43xx only)
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58 SPI (LPC43xx only)
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60 ADCHS (12-bit ADC) (LPC4370 only)
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Refer to NXP LPC18xx or LPC43xx user manual for more details about
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the reset signals and the connected block/peripheral.
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Reset provider example:
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rgu: reset-controller@40053000 {
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compatible = "nxp,lpc1850-rgu";
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reg = <0x40053000 0x1000>;
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clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
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clock-names = "delay", "reg";
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#reset-cells = <1>;
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};
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Reset consumer example:
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mac: ethernet@40010000 {
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compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
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reg = <0x40010000 0x2000>;
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interrupts = <5>;
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interrupt-names = "macirq";
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clocks = <&ccu1 CLK_CPU_ETHERNET>;
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clock-names = "stmmaceth";
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resets = <&rgu 22>;
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reset-names = "stmmaceth";
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};
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@ -0,0 +1,101 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP LPC1850 Reset Generation Unit (RGU)
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: nxp,lpc1850-rgu
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reg:
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maxItems: 1
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: delay
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- const: reg
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'#reset-cells':
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const: 1
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description: |
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See table below for valid peripheral reset numbers. Numbers not
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in the table below are either reserved or not applicable for
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normal operation.
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Reset Peripheral
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9 System control unit (SCU)
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12 ARM Cortex-M0 subsystem core (LPC43xx only)
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13 CPU core
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16 LCD controller
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17 USB0
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18 USB1
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19 DMA
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20 SDIO
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21 External memory controller (EMC)
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22 Ethernet
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25 Flash bank A
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27 EEPROM
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28 GPIO
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29 Flash bank B
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32 Timer0
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33 Timer1
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34 Timer2
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35 Timer3
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36 Repetitive Interrupt timer (RIT)
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37 State Configurable Timer (SCT)
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38 Motor control PWM (MCPWM)
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39 QEI
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40 ADC0
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41 ADC1
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42 DAC
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44 USART0
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45 UART1
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46 USART2
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47 USART3
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48 I2C0
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49 I2C1
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50 SSP0
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51 SSP1
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52 I2S0 and I2S1
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53 Serial Flash Interface (SPIFI)
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54 C_CAN1
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55 C_CAN0
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56 ARM Cortex-M0 application core (LPC4370 only)
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57 SGPIO (LPC43xx only)
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58 SPI (LPC43xx only)
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60 ADCHS (12-bit ADC) (LPC4370 only)
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Refer to NXP LPC18xx or LPC43xx user manual for more details about
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the reset signals and the connected block/peripheral.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/lpc18xx-ccu.h>
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#include <dt-bindings/clock/lpc18xx-cgu.h>
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reset-controller@40053000 {
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compatible = "nxp,lpc1850-rgu";
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reg = <0x40053000 0x1000>;
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clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
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clock-names = "delay", "reg";
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#reset-cells = <1>;
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};
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