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RISC-V Devicetrees for v6.20 (or v7.0) 

Anlogic:
 Minor change to the extension information, to add the "b" extension
 that's a catch-all for 3 of the extensions already in the dts.
 
 Starfive:
 Append the jh7110 compatible to jh7110s devicetrees, as that will enable
 OpenSBI etc to run without adding support for this minor variant. The
 "s" device differs from the non "s" device only in
 thermal limits and voltage/frequency characteristics.
 
 Microchip:
 Redo the mpfs clock setup yet again, to something approaching correct.
 The original binding conjured up for the platform was wildly inaccurate,
 and even with the original improvements, a bigger change to using
 syscons was required to support several peripherals that also inhabit
 the memory regions that the clocks lie in. The damage to the dts isn't
 that bad in the end, and of course the whole thing has been done in a
 backwards compatible manner, with the code changes being merged a cycle
 or two ago in the kernel and like a year ago in U-Boot (the only other
 user that I am aware of).
 
 Generic:
 Additions to extensions.yaml, mainly for things in the "rva23" profile
 that appear for the first time on the Spacemit K3 SoC.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.20 (or v7.0)

Anlogic:
Minor change to the extension information, to add the "b" extension
that's a catch-all for 3 of the extensions already in the dts.

Starfive:
Append the jh7110 compatible to jh7110s devicetrees, as that will enable
OpenSBI etc to run without adding support for this minor variant. The
"s" device differs from the non "s" device only in
thermal limits and voltage/frequency characteristics.

Microchip:
Redo the mpfs clock setup yet again, to something approaching correct.
The original binding conjured up for the platform was wildly inaccurate,
and even with the original improvements, a bigger change to using
syscons was required to support several peripherals that also inhabit
the memory regions that the clocks lie in. The damage to the dts isn't
that bad in the end, and of course the whole thing has been done in a
backwards compatible manner, with the code changes being merged a cycle
or two ago in the kernel and like a year ago in U-Boot (the only other
user that I am aware of).

Generic:
Additions to extensions.yaml, mainly for things in the "rva23" profile
that appear for the first time on the Spacemit K3 SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: anlogic: dr1v90: Add "b" ISA extension
  dt-bindings: riscv: extensions: Drop unnecessary select schema
  dt-bindings: riscv: Add Sha and its comprised extensions
  dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
  dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
  dt-bindings: riscv: Add B ISA extension description
  dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt
  riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board
  riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
  dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
  riscv: dts: microchip: convert clock and reset to use syscon
  riscv: dts: microchip: fix mailbox description

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-01-28 23:34:33 +01:00
parent b095c27fc8 18649ffbb6
commit 25ed1e9840
6 changed files with 210 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

194
Documentation/devicetree/bindings/riscv/extensions.yaml
View File

@ -24,12 +24,6 @@ description: |
ratified states, with the exception of the I, Zicntr & Zihpm extensions.
See the "i" property for more information.
select:
properties:
compatible:
contains:
const: riscv
properties:
riscv,isa:
description:
@ -109,6 +103,13 @@ properties:
The standard C extension for compressed instructions, as ratified in
the 20191213 version of the unprivileged ISA specification.
- const: b
description:
The standard B extension for bit manipulation instructions, as
ratified in the 20240411 version of the unprivileged ISA
specification. The B standard extension comprises instructions
provided by the Zba, Zbb, and Zbs extensions.
- const: v
description:
The standard V extension for vector operations, as ratified
@ -117,10 +118,62 @@ properties:
- const: h
description:
The standard H extension for hypervisors as ratified in the 20191213
version of the privileged ISA specification.
The standard H extension for hypervisors as ratified in the RISC-V
Instruction Set Manual, Volume II Privileged Architecture,
Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
- const: sha
description: |
The standard Sha extension for augmented hypervisor extension as
ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6
("rva23/rvb23 ratified").
Sha captures the full set of features that are mandated to be
supported along with the H extension. Sha comprises the following
extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
Shvstvecd, and Ssstateen.
- const: shcounterenw
description: |
The standard Shcounterenw extension for support writable enables
in hcounteren for any supported counter, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: shgatpa
description: |
The standard Shgatpa extension indicates that for each supported
virtual memory scheme SvNN supported in satp, the corresponding
hgatp SvNNx4 mode must be supported. The hgatp mode Bare must
also be supported. It is ratified in RISC-V Profiles Version 1.0,
with commit b1d806605f87 ("Updated to ratified state.")
- const: shtvala
description: |
The standard Shtvala extension for htval be written with the
faulting guest physical address in all circumstances permitted by
the ISA. It is ratified in RISC-V Profiles Version 1.0, with
commit b1d806605f87 ("Updated to ratified state.")
- const: shvsatpa
description: |
The standard Shvsatpa extension for vsatp supporting all translation
modes supported in satp, as ratified in RISC-V Profiles Version 1.0,
with commit b1d806605f87 ("Updated to ratified state.")
- const: shvstvala
description: |
The standard Shvstvala extension for vstval provides all needed
values as ratified in RISC-V Profiles Version 1.0, with commit
b1d806605f87 ("Updated to ratified state.")
- const: shvstvecd
description: |
The standard Shvstvecd extension for vstvec supporting Direct mode,
as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: smaia
description: |
The standard Smaia supervisor-level extension for the advanced
@ -153,24 +206,62 @@ properties:
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: ssccptr
description: |
The standard Ssccptr extension for main memory (cacheability and
coherence) hardware page-table reads, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
- const: sscounterenw
description: |
The standard Sscounterenw extension for support writable enables
in scounteren for any supported counter, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
- const: ssstateen
description: |
The standard Ssstateen extension for supervisor-mode view of the
state-enable extension, as ratified in RISC-V Profiles Version 1.0,
with commit b1d806605f87 ("Updated to ratified state.")
- const: sstc
description: |
The standard Sstc supervisor-level extension for time compare as
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
- const: sstvala
description: |
The standard Sstvala extension for stval provides all needed values
as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: sstvecd
description: |
The standard Sstvecd extension for stvec supports Direct mode as
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: ssu64xl
description: |
The standard Ssu64xl extension for UXLEN=64 must be supported, as
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
("Updated to ratified state.")
- const: svade
description: |
The standard Svade supervisor-level extension for SW-managed PTE A/D
@ -202,20 +293,22 @@ properties:
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
address-translation cache invalidation as ratified in the 20191213
version of the privileged ISA specification.
address-translation cache invalidation as ratified in the RISC-V
Instruction Set Manual, Volume II Privileged Architecture,
Document Version 20211203.
- const: svnapot
description:
The standard Svnapot supervisor-level extensions for napot
translation contiguity as ratified in the 20191213 version of the
privileged ISA specification.
translation contiguity as ratified in the RISC-V Instruction Set
Manual, Volume II Privileged Architecture, Document Version
20211203.
- const: svpbmt
description:
The standard Svpbmt supervisor-level extensions for page-based
memory types as ratified in the 20191213 version of the privileged
ISA specification.
memory types as ratified in the RISC-V Instruction Set Manual,
Volume II Privileged Architecture, Document Version 20211203.
- const: svrsw60t59b
description:
@ -230,6 +323,12 @@ properties:
as ratified at commit 4a69197e5617 ("Update to ratified state") of
riscv-svvptc.
- const: za64rs
description:
The standard Za64rs extension for reservation set size of at most
64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit
b1d806605f87 ("Updated to ratified state.")
- const: zaamo
description: |
The standard Zaamo extension for atomic memory operations as
@ -371,6 +470,27 @@ properties:
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
- const: ziccamoa
description:
The standard Ziccamoa extension for main memory (cacheability and
coherence) must support all atomics in A, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: ziccif
description:
The standard Ziccif extension for main memory (cacheability and
coherence) instruction fetch atomicity, as ratified in RISC-V
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: zicclsm
description:
The standard Zicclsm extension for main memory (cacheability and
coherence) must support misaligned loads and stores, as ratified
in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated
to ratified state.")
- const: ziccrse
description:
The standard Ziccrse extension which provides forward progress
@ -749,6 +869,42 @@ properties:
then:
contains:
const: f
# B comprises Zba, Zbb, and Zbs
- if:
contains:
const: b
then:
allOf:
- contains:
const: zba
- contains:
const: zbb
- contains:
const: zbs
# Zba, Zbb, Zbs together require B
- if:
allOf:
- contains:
const: zba
- contains:
const: zbb
- contains:
const: zbs
then:
contains:
const: b
# Za64rs and Ziccrse depend on Zalrsc or A
- if:
contains:
anyOf:
- const: za64rs
- const: ziccrse
then:
oneOf:
- contains:
const: zalrsc
- contains:
const: a
# Zcb depends on Zca
- if:
contains:
@ -790,6 +946,16 @@ properties:
then:
contains:
const: f
# Ziccamoa depends on Zaamo or A
- if:
contains:
const: ziccamoa
then:
oneOf:
- contains:
const: zaamo
- contains:
const: a
# Zvfbfmin depends on V or Zve32f
- if:
contains:

1
Documentation/devicetree/bindings/riscv/starfive.yaml
View File

@ -41,6 +41,7 @@ properties:
- starfive,visionfive-2-lite
- starfive,visionfive-2-lite-emmc
- const: starfive,jh7110s
- const: starfive,jh7110
additionalProperties: true

5
arch/riscv/boot/dts/anlogic/dr1v90.dtsi
View File

@ -27,8 +27,9 @@ cpu@0 {
mmu-type = "riscv,sv39";
reg = <0>;
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
"zbkc", "zbs", "zicntr", "zicsr", "zifencei",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
"zba", "zbb", "zbc", "zbkc", "zbs",
"zicntr", "zicsr", "zifencei",
"zihintpause", "zihpm";
cpu0_intc: interrupt-controller {

34
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -251,14 +251,17 @@ pdma: dma-controller@3000000 {
#dma-cells = <1>;
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
mss_top_sysreg: syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x0 0x20002000 0x0 0x1000>;
#reset-cells = <1>;
};
sysreg_scb: syscon@20003000 {
compatible = "microchip,mpfs-sysreg-scb", "syscon";
reg = <0x0 0x20003000 0x0 0x1000>;
};
ccc_se: clock-controller@38010000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
@ -447,7 +450,7 @@ mac0: ethernet@20110000 {
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC0>;
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
@ -461,7 +464,7 @@ mac1: ethernet@20112000 {
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC1>;
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
@ -521,10 +524,14 @@ usb: usb@20201000 {
status = "disabled";
};
mbox: mailbox@37020000 {
control_scb: syscon@37020000 {
compatible = "microchip,mpfs-control-scb", "syscon";
reg = <0x0 0x37020000 0x0 0x100>;
};
mbox: mailbox@37020800 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
<0x0 0x37020800 0x0 0x100>;
reg = <0x0 0x37020800 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;
@ -541,5 +548,12 @@ syscontroller_qspi: spi@37020100 {
clocks = <&scbclk>;
status = "disabled";
};
clkcfg: clkcfg@3e001000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x3e001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
};
};
};

2
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
View File

@ -9,7 +9,7 @@
/ {
model = "StarFive VisionFive 2 Lite eMMC";
compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";
compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {

2
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
View File

@ -9,7 +9,7 @@
/ {
model = "StarFive VisionFive 2 Lite";
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {