mirror of https://github.com/torvalds/linux.git
pwm: mediatek: Convert to waveform API
Implement the new waveform callbacks which makes the usage of this hardware more flexible and allows to use it via the pwm character device. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20251013114258.149260-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
This commit is contained in:
Uwe Kleine-König
Uwe Kleine-König
parent
0251fa8887
commit
24ec5632a1
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@ -135,50 +135,51 @@ static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
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num * chip->soc->chanreg_width + offset);
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num * chip->soc->chanreg_width + offset);
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}
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}
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static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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struct pwm_mediatek_waveform {
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{
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u32 enable;
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 con;
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u32 value;
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u32 width;
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u32 thres;
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value = readl(pc->regs);
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};
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value |= BIT(pwm->hwpwm);
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writel(value, pc->regs);
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static int pwm_mediatek_round_waveform_tohw(struct pwm_chip *chip, struct pwm_device *pwm,
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}
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const struct pwm_waveform *wf, void *_wfhw)
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static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 value;
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value = readl(pc->regs);
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value &= ~BIT(pwm->hwpwm);
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writel(value, pc->regs);
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}
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static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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u64 duty_ns, u64 period_ns)
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{
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{
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struct pwm_mediatek_waveform *wfhw = _wfhw;
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 clkdiv, enable;
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u32 clkdiv, enable;
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u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
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u64 cnt_period, cnt_duty;
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u64 cnt_period, cnt_duty;
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unsigned long clk_rate;
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unsigned long clk_rate;
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int ret;
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int ret = 0;
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ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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if (wf->period_length_ns == 0) {
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if (ret < 0)
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*wfhw = (typeof(*wfhw)){
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return ret;
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.enable = 0,
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};
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return 0;
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}
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if (!pc->clk_pwms[pwm->hwpwm].rate) {
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struct clk *clk = pc->clk_pwms[pwm->hwpwm].clk;
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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pc->clk_pwms[pwm->hwpwm].rate = clk_get_rate(clk);
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clk_disable_unprepare(clk);
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}
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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if (clk_rate == 0 || clk_rate > 1000000000)
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return -EINVAL;
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/* Make sure we use the bus clock and not the 26MHz clock */
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cnt_period = mul_u64_u64_div_u64(wf->period_length_ns, clk_rate, NSEC_PER_SEC);
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if (pc->soc->pwm_ck_26m_sel_reg)
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writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
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cnt_period = mul_u64_u64_div_u64(period_ns, clk_rate, NSEC_PER_SEC);
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if (cnt_period == 0) {
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if (cnt_period == 0) {
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ret = -ERANGE;
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cnt_period = 1;
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goto out;
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ret = 1;
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}
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}
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if (cnt_period > FIELD_MAX(PWMDWIDTH_PERIOD) + 1) {
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if (cnt_period > FIELD_MAX(PWMDWIDTH_PERIOD) + 1) {
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@ -193,7 +194,7 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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clkdiv = 0;
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clkdiv = 0;
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}
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}
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cnt_duty = mul_u64_u64_div_u64(duty_ns, clk_rate, NSEC_PER_SEC) >> clkdiv;
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cnt_duty = mul_u64_u64_div_u64(wf->duty_length_ns, clk_rate, NSEC_PER_SEC) >> clkdiv;
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if (cnt_duty > cnt_period)
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if (cnt_duty > cnt_period)
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cnt_duty = cnt_period;
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cnt_duty = cnt_period;
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@ -206,26 +207,173 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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cnt_period -= 1;
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cnt_period -= 1;
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dev_dbg(&chip->dev, "pwm#%u: %lld/%lld @%lu -> CON: %x, PERIOD: %llx, DUTY: %llx\n",
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dev_dbg(&chip->dev, "pwm#%u: %lld/%lld @%lu -> ENABLE: %x, CON: %x, PERIOD: %llx, DUTY: %llx\n",
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pwm->hwpwm, duty_ns, period_ns, clk_rate, clkdiv, cnt_period, cnt_duty);
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pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, clk_rate,
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enable, clkdiv, cnt_period, cnt_duty);
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*wfhw = (typeof(*wfhw)){
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.enable = enable,
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.con = clkdiv,
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.width = cnt_period,
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.thres = cnt_duty,
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};
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return ret;
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}
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static int pwm_mediatek_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
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const void *_wfhw, struct pwm_waveform *wf)
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{
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const struct pwm_mediatek_waveform *wfhw = _wfhw;
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 clkdiv, cnt_period, cnt_duty;
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unsigned long clk_rate;
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/*
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* When _wfhw was populated, the clock was on, so .rate is
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* already set appropriately.
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*/
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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if (wfhw->enable) {
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clkdiv = FIELD_GET(PWMCON_CLKDIV, wfhw->con);
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cnt_period = FIELD_GET(PWMDWIDTH_PERIOD, wfhw->width);
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cnt_duty = FIELD_GET(PWMTHRES_DUTY, wfhw->thres);
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if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
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/*
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* cnt_period is a 13 bit value, NSEC_PER_SEC is 30 bits wide
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* from the other PWMs on MT7623.
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* and clkdiv is less than 8, so the multiplication doesn't
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* overflow an u64.
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*/
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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*wf = (typeof(*wf)){
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reg_thres = PWM45THRES_FIXUP;
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.period_length_ns =
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}
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DIV_ROUND_UP_ULL((u64)(cnt_period + 1) * NSEC_PER_SEC << clkdiv, clk_rate),
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.duty_length_ns =
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DIV_ROUND_UP_ULL((u64)(cnt_duty + 1) * NSEC_PER_SEC << clkdiv, clk_rate),
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};
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} else {
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clkdiv = 0;
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cnt_period = 0;
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cnt_duty = 0;
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pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
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/*
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
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* .enable = 0 is also used for too small duty_cycle values, so
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* report the HW as being enabled to communicate the minimal
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* period.
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*/
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*wf = (typeof(*wf)){
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.period_length_ns =
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DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate),
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.duty_length_ns = 0,
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};
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};
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dev_dbg(&chip->dev, "pwm#%u: ENABLE: %x, CLKDIV: %x, PERIOD: %x, DUTY: %x @%lu -> %lld/%lld\n",
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pwm->hwpwm, wfhw->enable, clkdiv, cnt_period, cnt_duty, clk_rate,
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wf->duty_length_ns, wf->period_length_ns);
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return 0;
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}
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static int pwm_mediatek_read_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm, void *_wfhw)
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{
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struct pwm_mediatek_waveform *wfhw = _wfhw;
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 enable, clkdiv, cnt_period, cnt_duty;
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u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
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int ret;
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ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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if (ret < 0)
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return ret;
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enable = readl(pc->regs) & BIT(pwm->hwpwm);
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if (enable) {
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if (enable) {
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
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if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
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pwm_mediatek_enable(chip, pwm);
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* from the other PWMs on MT7623.
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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reg_thres = PWM45THRES_FIXUP;
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}
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clkdiv = FIELD_GET(PWMCON_CLKDIV, pwm_mediatek_readl(pc, pwm->hwpwm, PWMCON));
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cnt_period = FIELD_GET(PWMDWIDTH_PERIOD, pwm_mediatek_readl(pc, pwm->hwpwm, reg_width));
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cnt_duty = FIELD_GET(PWMTHRES_DUTY, pwm_mediatek_readl(pc, pwm->hwpwm, reg_thres));
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*wfhw = (typeof(*wfhw)){
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.enable = enable,
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.con = BIT(15) | clkdiv,
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.width = cnt_period,
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.thres = cnt_duty,
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};
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} else {
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} else {
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pwm_mediatek_disable(chip, pwm);
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*wfhw = (typeof(*wfhw)){
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.enable = 0,
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};
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}
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pwm_mediatek_clk_disable(pc, pwm->hwpwm);
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return ret;
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}
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static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
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struct pwm_device *pwm, const void *_wfhw)
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{
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const struct pwm_mediatek_waveform *wfhw = _wfhw;
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 ctrl;
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int ret;
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ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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if (ret < 0)
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return ret;
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ctrl = readl(pc->regs);
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if (wfhw->enable) {
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u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
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if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* from the other PWMs on MT7623.
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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reg_thres = PWM45THRES_FIXUP;
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}
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if (!(ctrl & BIT(pwm->hwpwm))) {
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/*
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* The clks are already on, just increasing the usage
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* counter doesn't fail.
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*/
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ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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if (unlikely(ret < 0))
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goto out;
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ctrl |= BIT(pwm->hwpwm);
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writel(ctrl, pc->regs);
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}
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/* Make sure we use the bus clock and not the 26MHz clock */
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if (pc->soc->pwm_ck_26m_sel_reg)
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writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
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pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | wfhw->con);
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, wfhw->width);
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, wfhw->thres);
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} else {
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if (ctrl & BIT(pwm->hwpwm)) {
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ctrl &= ~BIT(pwm->hwpwm);
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writel(ctrl, pc->regs);
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pwm_mediatek_clk_disable(pc, pwm->hwpwm);
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}
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}
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}
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out:
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out:
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@ -234,93 +382,12 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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return ret;
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return ret;
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}
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}
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static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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int err;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (!state->enabled) {
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if (pwm->state.enabled) {
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pwm_mediatek_disable(chip, pwm);
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pwm_mediatek_clk_disable(pc, pwm->hwpwm);
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}
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return 0;
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}
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err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
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if (err)
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return err;
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if (!pwm->state.enabled)
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err = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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return err;
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}
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static int pwm_mediatek_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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int ret;
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u32 enable;
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u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
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if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* from the other PWMs on MT7623.
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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reg_thres = PWM45THRES_FIXUP;
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}
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ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
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if (ret < 0)
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return ret;
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enable = readl(pc->regs);
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if (enable & BIT(pwm->hwpwm)) {
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u32 clkdiv, cnt_period, cnt_duty;
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unsigned long clk_rate;
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clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
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state->enabled = true;
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state->polarity = PWM_POLARITY_NORMAL;
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clkdiv = FIELD_GET(PWMCON_CLKDIV,
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pwm_mediatek_readl(pc, pwm->hwpwm, PWMCON));
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cnt_period = FIELD_GET(PWMDWIDTH_PERIOD,
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pwm_mediatek_readl(pc, pwm->hwpwm, reg_width));
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cnt_duty = FIELD_GET(PWMTHRES_DUTY,
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pwm_mediatek_readl(pc, pwm->hwpwm, reg_thres));
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/*
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|
||||||
* cnt_period is a 13 bit value, NSEC_PER_SEC is 30 bits wide
|
|
||||||
* and clkdiv is less than 8, so the multiplication doesn't
|
|
||||||
* overflow an u64.
|
|
||||||
*/
|
|
||||||
state->period =
|
|
||||||
DIV_ROUND_UP_ULL((u64)cnt_period * NSEC_PER_SEC << clkdiv, clk_rate);
|
|
||||||
state->duty_cycle =
|
|
||||||
DIV_ROUND_UP_ULL((u64)cnt_duty * NSEC_PER_SEC << clkdiv, clk_rate);
|
|
||||||
} else {
|
|
||||||
state->enabled = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
pwm_mediatek_clk_disable(pc, pwm->hwpwm);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct pwm_ops pwm_mediatek_ops = {
|
static const struct pwm_ops pwm_mediatek_ops = {
|
||||||
.apply = pwm_mediatek_apply,
|
.sizeof_wfhw = sizeof(struct pwm_mediatek_waveform),
|
||||||
.get_state = pwm_mediatek_get_state,
|
.round_waveform_tohw = pwm_mediatek_round_waveform_tohw,
|
||||||
|
.round_waveform_fromhw = pwm_mediatek_round_waveform_fromhw,
|
||||||
|
.read_waveform = pwm_mediatek_read_waveform,
|
||||||
|
.write_waveform = pwm_mediatek_write_waveform,
|
||||||
};
|
};
|
||||||
|
|
||||||
static int pwm_mediatek_init_used_clks(struct pwm_mediatek_chip *pc)
|
static int pwm_mediatek_init_used_clks(struct pwm_mediatek_chip *pc)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue