mirror of https://github.com/torvalds/linux.git
dmaengine: tegra210-adma: Add Tegra264 support
Add Tegra264 ADMA support with following changes: - Add soc_data for Tegra264-specific variations. - Tegra264 supports 64 channels and 10 pages, hence update the global page configuration. - In Tegra264 FIFO and outstanding request configs are moved to global registers, hence add those registers offset in adma channel struct. Also, 'has_outstanding_reqs' is removed and configuration moved to the SoC data. - Update channel direction and mode bit positions as per Tegra264. - Register offsets are updated to align with Tegra264. Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://lore.kernel.org/r/20250512050010.1025259-3-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sheetal
Vinod Koul
parent
b81cd165e4
commit
21e1273877
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@ -27,10 +27,10 @@
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#define ADMA_CH_INT_CLEAR 0x1c
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#define ADMA_CH_CTRL 0x24
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#define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
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#define ADMA_CH_CTRL_DIR(val, mask, shift) (((val) & (mask)) << (shift))
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#define ADMA_CH_CTRL_DIR_AHUB2MEM 2
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#define ADMA_CH_CTRL_DIR_MEM2AHUB 4
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#define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
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#define ADMA_CH_CTRL_MODE_CONTINUOUS(shift) (2 << (shift))
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#define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
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#define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
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@ -41,15 +41,27 @@
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#define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
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#define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
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#define ADMA_CH_CONFIG_MAX_BUFS 8
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#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
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#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 4)
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#define ADMA_GLOBAL_CH_CONFIG 0x400
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#define ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0x7)
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#define ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 8)
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#define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30
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#define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70
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#define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84
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#define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 0x44
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#define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 0x48
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#define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 0x100
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#define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 0x104
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#define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 0x180
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#define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 0x184
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#define TEGRA264_ADMA_GLOBAL_PAGE_OFFSET 0x8
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#define ADMA_CH_FIFO_CTRL 0x2c
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#define ADMA_CH_TX_FIFO_SIZE_SHIFT 8
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#define ADMA_CH_RX_FIFO_SIZE_SHIFT 0
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#define ADMA_GLOBAL_CH_FIFO_CTRL 0x300
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#define ADMA_CH_LOWER_SRC_ADDR 0x34
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#define ADMA_CH_LOWER_TRG_ADDR 0x3c
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@ -73,36 +85,48 @@ struct tegra_adma;
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* @adma_get_burst_config: Function callback used to set DMA burst size.
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* @global_reg_offset: Register offset of DMA global register.
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* @global_int_clear: Register offset of DMA global interrupt clear.
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* @global_ch_fifo_base: Global channel fifo ctrl base offset
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* @global_ch_config_base: Global channel config base offset
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* @ch_req_tx_shift: Register offset for AHUB transmit channel select.
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* @ch_req_rx_shift: Register offset for AHUB receive channel select.
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* @ch_dir_shift: Channel direction bit position.
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* @ch_mode_shift: Channel mode bit position.
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* @ch_base_offset: Register offset of DMA channel registers.
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* @ch_tc_offset_diff: From TC register onwards offset differs for Tegra264
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* @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
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* @ch_config: Outstanding and WRR config values
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* @ch_req_mask: Mask for Tx or Rx channel select.
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* @ch_dir_mask: Mask for channel direction.
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* @ch_req_max: Maximum number of Tx or Rx channels available.
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* @ch_reg_size: Size of DMA channel register space.
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* @nr_channels: Number of DMA channels available.
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* @ch_fifo_size_mask: Mask for FIFO size field.
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* @sreq_index_offset: Slave channel index offset.
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* @max_page: Maximum ADMA Channel Page.
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* @has_outstanding_reqs: If DMA channel can have outstanding requests.
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* @set_global_pg_config: Global page programming.
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*/
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struct tegra_adma_chip_data {
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unsigned int (*adma_get_burst_config)(unsigned int burst_size);
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unsigned int global_reg_offset;
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unsigned int global_int_clear;
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unsigned int global_ch_fifo_base;
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unsigned int global_ch_config_base;
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unsigned int ch_req_tx_shift;
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unsigned int ch_req_rx_shift;
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unsigned int ch_dir_shift;
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unsigned int ch_mode_shift;
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unsigned int ch_base_offset;
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unsigned int ch_tc_offset_diff;
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unsigned int ch_fifo_ctrl;
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unsigned int ch_config;
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unsigned int ch_req_mask;
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unsigned int ch_dir_mask;
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unsigned int ch_req_max;
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unsigned int ch_reg_size;
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unsigned int nr_channels;
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unsigned int ch_fifo_size_mask;
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unsigned int sreq_index_offset;
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unsigned int max_page;
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bool has_outstanding_reqs;
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void (*set_global_pg_config)(struct tegra_adma *tdma);
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};
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@ -112,6 +136,7 @@ struct tegra_adma_chip_data {
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struct tegra_adma_chan_regs {
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unsigned int ctrl;
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unsigned int config;
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unsigned int global_config;
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unsigned int src_addr;
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unsigned int trg_addr;
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unsigned int fifo_ctrl;
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@ -150,6 +175,9 @@ struct tegra_adma_chan {
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/* Transfer count and position info */
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unsigned int tx_buf_count;
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unsigned int tx_buf_pos;
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unsigned int global_ch_fifo_offset;
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unsigned int global_ch_config_offset;
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};
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/*
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@ -246,6 +274,29 @@ static void tegra186_adma_global_page_config(struct tegra_adma *tdma)
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tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0x4), 0xffffff);
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}
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static void tegra264_adma_global_page_config(struct tegra_adma *tdma)
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{
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u32 global_page_offset = tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_OFFSET;
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/* If the default page (page1) is not used, then clear page1 registers */
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if (tdma->ch_page_no) {
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0, 0);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1, 0);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0, 0);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1, 0);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0, 0);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1, 0);
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}
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/* Program global registers for selected page */
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, 0xffffffff);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, 0xffffffff);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset, 0xffffffff);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset, 0x1);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset, 0xffffffff);
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tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset, 0x1);
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}
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static int tegra_adma_init(struct tegra_adma *tdma)
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{
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u32 status;
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@ -404,11 +455,21 @@ static void tegra_adma_start(struct tegra_adma_chan *tdc)
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tdc->tx_buf_pos = 0;
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tdc->tx_buf_count = 0;
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tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
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tdma_ch_write(tdc, ADMA_CH_TC - tdc->tdma->cdata->ch_tc_offset_diff, ch_regs->tc);
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tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
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tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
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tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
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tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
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tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdc->tdma->cdata->ch_tc_offset_diff,
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ch_regs->src_addr);
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tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdc->tdma->cdata->ch_tc_offset_diff,
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ch_regs->trg_addr);
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if (!tdc->tdma->cdata->global_ch_fifo_base)
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tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
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else if (tdc->global_ch_fifo_offset)
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tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_regs->fifo_ctrl);
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if (tdc->global_ch_config_offset)
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tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_regs->global_config);
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tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
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/* Start ADMA */
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@ -421,7 +482,8 @@ static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
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{
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struct tegra_adma_desc *desc = tdc->desc;
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unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
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unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
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unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS -
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tdc->tdma->cdata->ch_tc_offset_diff);
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unsigned int periods_remaining;
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/*
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@ -627,13 +689,16 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
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return -EINVAL;
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}
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ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
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ADMA_CH_CTRL_MODE_CONTINUOUS |
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ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir, cdata->ch_dir_mask,
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cdata->ch_dir_shift) |
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ADMA_CH_CTRL_MODE_CONTINUOUS(cdata->ch_mode_shift) |
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ADMA_CH_CTRL_FLOWCTRL_EN;
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ch_regs->config |= cdata->adma_get_burst_config(burst_size);
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ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
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if (cdata->has_outstanding_reqs)
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ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
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if (cdata->global_ch_config_base)
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ch_regs->global_config |= cdata->ch_config;
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else
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ch_regs->config |= cdata->ch_config;
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/*
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* 'sreq_index' represents the current ADMAIF channel number and as per
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@ -788,12 +853,23 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)
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/* skip if channel is not active */
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if (!ch_reg->cmd)
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continue;
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ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
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ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
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ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
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ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff);
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ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR -
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tdma->cdata->ch_tc_offset_diff);
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ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR -
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tdma->cdata->ch_tc_offset_diff);
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ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
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ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
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if (tdc->global_ch_config_offset)
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ch_reg->global_config = tdma_read(tdc->tdma, tdc->global_ch_config_offset);
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if (!tdc->tdma->cdata->global_ch_fifo_base)
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ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
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else if (tdc->global_ch_fifo_offset)
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ch_reg->fifo_ctrl = tdma_read(tdc->tdma, tdc->global_ch_fifo_offset);
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ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
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}
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clk_disable:
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@ -832,12 +908,23 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)
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/* skip if channel was not active earlier */
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if (!ch_reg->cmd)
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continue;
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tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
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tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
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tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
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tdma_ch_write(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff, ch_reg->tc);
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tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdma->cdata->ch_tc_offset_diff,
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ch_reg->src_addr);
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tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdma->cdata->ch_tc_offset_diff,
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ch_reg->trg_addr);
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tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
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tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
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if (!tdc->tdma->cdata->global_ch_fifo_base)
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tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
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else if (tdc->global_ch_fifo_offset)
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tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_reg->fifo_ctrl);
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if (tdc->global_ch_config_offset)
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tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_reg->global_config);
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tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
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tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
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}
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@ -848,17 +935,23 @@ static const struct tegra_adma_chip_data tegra210_chip_data = {
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.adma_get_burst_config = tegra210_adma_get_burst_config,
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.global_reg_offset = 0xc00,
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.global_int_clear = 0x20,
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.global_ch_fifo_base = 0,
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.global_ch_config_base = 0,
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.ch_req_tx_shift = 28,
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.ch_req_rx_shift = 24,
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.ch_dir_shift = 12,
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.ch_mode_shift = 8,
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.ch_base_offset = 0,
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.ch_tc_offset_diff = 0,
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.ch_config = ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1),
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.ch_req_mask = 0xf,
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.ch_dir_mask = 0xf,
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.ch_req_max = 10,
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.ch_reg_size = 0x80,
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.nr_channels = 22,
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.ch_fifo_size_mask = 0xf,
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.sreq_index_offset = 2,
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.max_page = 0,
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.has_outstanding_reqs = false,
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.set_global_pg_config = NULL,
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};
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@ -866,23 +959,56 @@ static const struct tegra_adma_chip_data tegra186_chip_data = {
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.adma_get_burst_config = tegra186_adma_get_burst_config,
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.global_reg_offset = 0,
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.global_int_clear = 0x402c,
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.global_ch_fifo_base = 0,
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.global_ch_config_base = 0,
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.ch_req_tx_shift = 27,
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.ch_req_rx_shift = 22,
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.ch_dir_shift = 12,
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.ch_mode_shift = 8,
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.ch_base_offset = 0x10000,
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.ch_tc_offset_diff = 0,
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.ch_config = ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1) |
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TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8),
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.ch_req_mask = 0x1f,
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.ch_dir_mask = 0xf,
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.ch_req_max = 20,
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.ch_reg_size = 0x100,
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.nr_channels = 32,
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.ch_fifo_size_mask = 0x1f,
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.sreq_index_offset = 4,
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.max_page = 4,
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.has_outstanding_reqs = true,
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.set_global_pg_config = tegra186_adma_global_page_config,
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};
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static const struct tegra_adma_chip_data tegra264_chip_data = {
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.adma_get_burst_config = tegra186_adma_get_burst_config,
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.global_reg_offset = 0,
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.global_int_clear = 0x800c,
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.global_ch_fifo_base = ADMA_GLOBAL_CH_FIFO_CTRL,
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.global_ch_config_base = ADMA_GLOBAL_CH_CONFIG,
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.ch_req_tx_shift = 26,
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.ch_req_rx_shift = 20,
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.ch_dir_shift = 10,
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.ch_mode_shift = 7,
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.ch_base_offset = 0x10000,
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.ch_tc_offset_diff = 4,
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.ch_config = ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(1) |
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ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(8),
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.ch_req_mask = 0x3f,
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.ch_dir_mask = 7,
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.ch_req_max = 32,
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.ch_reg_size = 0x100,
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.nr_channels = 64,
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.ch_fifo_size_mask = 0x7f,
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.sreq_index_offset = 0,
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.max_page = 10,
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.set_global_pg_config = tegra264_adma_global_page_config,
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};
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static const struct of_device_id tegra_adma_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
|
||||
{ .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
|
||||
{ .compatible = "nvidia,tegra264-adma", .data = &tegra264_chip_data },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
|
||||
|
|
@ -985,6 +1111,15 @@ static int tegra_adma_probe(struct platform_device *pdev)
|
|||
|
||||
tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i);
|
||||
|
||||
if (tdma->base_addr) {
|
||||
if (cdata->global_ch_fifo_base)
|
||||
tdc->global_ch_fifo_offset = cdata->global_ch_fifo_base + (4 * i);
|
||||
|
||||
if (cdata->global_ch_config_base)
|
||||
tdc->global_ch_config_offset =
|
||||
cdata->global_ch_config_base + (4 * i);
|
||||
}
|
||||
|
||||
tdc->irq = of_irq_get(pdev->dev.of_node, i);
|
||||
if (tdc->irq <= 0) {
|
||||
ret = tdc->irq ?: -ENXIO;
|
||||
|
|
|
|||
Loading…
Reference in New Issue