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riscv: Add xmipsexectl instructions 

Add xmipsexectl instruction opcodes. This includes the MIPS.PAUSE,
MIPS.EHB, and MIPS.IHB instructions.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-3-a6cbbe1c3412@htecgroup.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Aleksa Paunovic 2025-07-24 17:23:27 +02:00 committed by Paul Walmsley
parent a8fed1bc03
commit 1d4ce63e33
1 changed files with 19 additions and 0 deletions
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19
arch/riscv/include/asm/vendor_extensions/mips.h
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@ -15,4 +15,23 @@ struct riscv_isa_vendor_ext_data_list;
extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
#endif
/* Extension specific instructions */
/*
* All of the xmipsexectl extension instructions are
* ‘hint’ encodings of the SLLI instruction,
* with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB,
* and imm = 5 for PAUSE.
* MIPS.PAUSE is an alternative opcode which is implemented to have the
* same behavior as PAUSE on some MIPS RISCV cores.
* MIPS.EHB clears all execution hazards before allowing
* any subsequent instructions to execute.
* MIPS.IHB clears all instruction hazards before
* allowing any subsequent instructions to fetch.
*/
#define MIPS_PAUSE ".4byte 0x00501013\n\t"
#define MIPS_EHB ".4byte 0x00301013\n\t"
#define MIPS_IHB ".4byte 0x00101013\n\t"
#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H