mirror of https://github.com/torvalds/linux.git
drm/i915/ddi: split up intel_ddi_read_func_ctl() by output type
The function has become quite long, and the switch-case statement quite complex with the fallthrougs. Simplify by splitting to individual functions and an if-ladder. This highlights how TRANS_DDI_MODE_SELECT_FDI_OR_128B132B works on different platforms. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2621df6e6b0b7ac75159cfb112755c35b30ce906.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
parent
f64a06540c
commit
1013ed6a62
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@ -3908,15 +3908,122 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
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crtc_state->sync_mode_slaves_mask);
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}
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static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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u32 ddi_func_ctl)
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{
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struct intel_display *display = to_intel_display(encoder);
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crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
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if (DISPLAY_VER(display) >= 14)
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crtc_state->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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else
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crtc_state->lane_count = 4;
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}
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static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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u32 ddi_func_ctl)
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{
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crtc_state->has_hdmi_sink = true;
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crtc_state->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, crtc_state);
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if (crtc_state->infoframes.enable)
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crtc_state->has_infoframe = true;
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if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
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crtc_state->hdmi_scrambling = true;
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if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
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crtc_state->hdmi_high_tmds_clock_ratio = true;
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intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
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}
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static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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u32 ddi_func_ctl)
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{
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struct intel_display *display = to_intel_display(encoder);
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crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
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crtc_state->enhanced_framing =
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intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
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DP_TP_CTL_ENHANCED_FRAME_ENABLE;
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}
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static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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u32 ddi_func_ctl)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (encoder->type == INTEL_OUTPUT_EDP)
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crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
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else
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crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
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crtc_state->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
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intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
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crtc_state->enhanced_framing =
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intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
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DP_TP_CTL_ENHANCED_FRAME_ENABLE;
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if (DISPLAY_VER(display) >= 11)
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crtc_state->fec_enable =
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intel_de_read(display,
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dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
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if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
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crtc_state->infoframes.enable |=
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intel_lspcon_infoframes_enabled(encoder, crtc_state);
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else
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crtc_state->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, crtc_state);
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}
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static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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u32 ddi_func_ctl)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
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crtc_state->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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if (DISPLAY_VER(display) >= 12)
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crtc_state->mst_master_transcoder =
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REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
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intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
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if (DISPLAY_VER(display) >= 11)
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crtc_state->fec_enable =
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intel_de_read(display,
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dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
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crtc_state->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, crtc_state);
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}
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static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
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struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
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u32 ddi_func_ctl, flags = 0;
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u32 ddi_func_ctl, ddi_mode, flags = 0;
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ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
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if (ddi_func_ctl & TRANS_DDI_PHSYNC)
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@ -3947,90 +4054,19 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
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break;
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}
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switch (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) {
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case TRANS_DDI_MODE_SELECT_HDMI:
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pipe_config->has_hdmi_sink = true;
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ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK;
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pipe_config->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, pipe_config);
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if (pipe_config->infoframes.enable)
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pipe_config->has_infoframe = true;
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if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
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pipe_config->hdmi_scrambling = true;
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if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
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pipe_config->hdmi_high_tmds_clock_ratio = true;
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fallthrough;
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case TRANS_DDI_MODE_SELECT_DVI:
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pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
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if (DISPLAY_VER(dev_priv) >= 14)
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pipe_config->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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else
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pipe_config->lane_count = 4;
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break;
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case TRANS_DDI_MODE_SELECT_DP_SST:
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if (encoder->type == INTEL_OUTPUT_EDP)
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pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
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else
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
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pipe_config->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
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&pipe_config->dp_m_n);
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intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
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&pipe_config->dp_m2_n2);
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pipe_config->enhanced_framing =
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intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
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DP_TP_CTL_ENHANCED_FRAME_ENABLE;
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if (DISPLAY_VER(dev_priv) >= 11)
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pipe_config->fec_enable =
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intel_de_read(dev_priv,
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dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
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if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
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pipe_config->infoframes.enable |=
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intel_lspcon_infoframes_enabled(encoder, pipe_config);
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else
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pipe_config->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, pipe_config);
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break;
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case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
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if (!HAS_DP20(display)) {
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/* FDI */
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pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
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pipe_config->enhanced_framing =
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intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
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DP_TP_CTL_ENHANCED_FRAME_ENABLE;
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break;
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}
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fallthrough; /* 128b/132b */
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case TRANS_DDI_MODE_SELECT_DP_MST:
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
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pipe_config->lane_count =
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((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
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if (DISPLAY_VER(dev_priv) >= 12)
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pipe_config->mst_master_transcoder =
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REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
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intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
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&pipe_config->dp_m_n);
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if (DISPLAY_VER(dev_priv) >= 11)
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pipe_config->fec_enable =
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intel_de_read(dev_priv,
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dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
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pipe_config->infoframes.enable |=
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intel_hdmi_infoframes_enabled(encoder, pipe_config);
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break;
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default:
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break;
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if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) {
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intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl);
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} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
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intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl);
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} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
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intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
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} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
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intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
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} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
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(ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) {
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intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
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}
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}
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