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x86/ibt: Optimize the FineIBT instruction sequence
Scott notes that non-taken branches are faster. Abuse overlapping code that traps instead of explicit UD2 instructions. And LEA does not modify flags and will have less dependencies. Suggested-by: Scott Constable <scott.d.constable@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Kees Cook <kees@kernel.org> Link: https://lore.kernel.org/r/20250224124200.371942555@infradead.org
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@ -1057,9 +1057,9 @@ early_param("cfi", cfi_parse_cmdline);
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* __cfi_\func: __cfi_\func:
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* movl $0x12345678,%eax // 5 endbr64 // 4
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* nop subl $0x12345678,%r10d // 7
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* nop jz 1f // 2
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* nop ud2 // 2
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* nop 1: nop // 1
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* nop jne __cfi_\func+6 // 2
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* nop nop3 // 3
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* nop
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* nop
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* nop
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* nop
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@ -1071,37 +1071,50 @@ early_param("cfi", cfi_parse_cmdline);
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*
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* caller: caller:
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* movl $(-0x12345678),%r10d // 6 movl $0x12345678,%r10d // 6
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* addl $-15(%r11),%r10d // 4 sub $16,%r11 // 4
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* addl $-15(%r11),%r10d // 4 lea -0x10(%r11),%r11 // 4
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* je 1f // 2 nop4 // 4
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* ud2 // 2
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* 1: call __x86_indirect_thunk_r11 // 5 call *%r11; nop2; // 5
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* 1: cs call __x86_indirect_thunk_r11 // 6 call *%r11; nop3; // 6
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*
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*/
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asm( ".pushsection .rodata \n"
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"fineibt_preamble_start: \n"
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" endbr64 \n"
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" subl $0x12345678, %r10d \n"
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" je fineibt_preamble_end \n"
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"fineibt_preamble_ud2: \n"
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" ud2 \n"
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" nop \n"
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"fineibt_preamble_end: \n"
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/*
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* <fineibt_preamble_start>:
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* 0: f3 0f 1e fa endbr64
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* 4: 41 81 <ea> 78 56 34 12 sub $0x12345678, %r10d
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* b: 75 f9 jne 6 <fineibt_preamble_start+0x6>
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* d: 0f 1f 00 nopl (%rax)
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*
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* Note that the JNE target is the 0xEA byte inside the SUB, this decodes as
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* (bad) on x86_64 and raises #UD.
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*/
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asm( ".pushsection .rodata \n"
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"fineibt_preamble_start: \n"
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" endbr64 \n"
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" subl $0x12345678, %r10d \n"
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" jne fineibt_preamble_start+6 \n"
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ASM_NOP3
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"fineibt_preamble_end: \n"
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".popsection\n"
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);
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extern u8 fineibt_preamble_start[];
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extern u8 fineibt_preamble_ud2[];
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extern u8 fineibt_preamble_end[];
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#define fineibt_preamble_size (fineibt_preamble_end - fineibt_preamble_start)
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#define fineibt_preamble_ud2 (fineibt_preamble_ud2 - fineibt_preamble_start)
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#define fineibt_preamble_ud 6
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#define fineibt_preamble_hash 7
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/*
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* <fineibt_caller_start>:
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* 0: 41 ba 78 56 34 12 mov $0x12345678, %r10d
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* 6: 4d 8d 5b f0 lea -0x10(%r11), %r11
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* a: 0f 1f 40 00 nopl 0x0(%rax)
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*/
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asm( ".pushsection .rodata \n"
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"fineibt_caller_start: \n"
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" movl $0x12345678, %r10d \n"
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" sub $16, %r11 \n"
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" lea -0x10(%r11), %r11 \n"
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ASM_NOP4
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"fineibt_caller_end: \n"
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".popsection \n"
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@ -1432,15 +1445,15 @@ static void poison_cfi(void *addr)
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}
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/*
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* regs->ip points to a UD2 instruction, return true and fill out target and
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* type when this UD2 is from a FineIBT preamble.
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* When regs->ip points to a 0xEA byte in the FineIBT preamble,
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* return true and fill out target and type.
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*
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* We check the preamble by checking for the ENDBR instruction relative to the
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* UD2 instruction.
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* 0xEA instruction.
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*/
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bool decode_fineibt_insn(struct pt_regs *regs, unsigned long *target, u32 *type)
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{
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unsigned long addr = regs->ip - fineibt_preamble_ud2;
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unsigned long addr = regs->ip - fineibt_preamble_ud;
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u32 hash;
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if (!exact_endbr((void *)addr))
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@ -1451,6 +1464,12 @@ bool decode_fineibt_insn(struct pt_regs *regs, unsigned long *target, u32 *type)
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__get_kernel_nofault(&hash, addr + fineibt_preamble_hash, u32, Efault);
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*type = (u32)regs->r10 + hash;
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/*
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* Since regs->ip points to the middle of an instruction; it cannot
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* continue with the normal fixup.
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*/
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regs->ip = *target;
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return true;
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Efault:
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@ -417,9 +417,8 @@ static void emit_fineibt(u8 **pprog, u32 hash)
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EMIT_ENDBR();
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EMIT3_off32(0x41, 0x81, 0xea, hash); /* subl $hash, %r10d */
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EMIT2(0x74, 0x07); /* jz.d8 +7 */
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EMIT2(0x0f, 0x0b); /* ud2 */
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EMIT1(0x90); /* nop */
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EMIT2(0x75, 0xf9); /* jne.d8 .-7 */
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EMIT3(0x0f, 0x1f, 0x00); /* nop3 */
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EMIT_ENDBR_POISON();
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*pprog = prog;
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