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dt-bindings: ethernet: eswin: fix yaml schema issues 

eswin,hsp-sp-csr attribute is one phandle with multiple arguments,
so the syntax should be in the form of:
 items:
   - items:
       - description: ...
       - description: ...
       - description: ...
       - description: ...

To align with the description of the 'eswin-sp-csr'
attribute in the mmc,usb modules, the description
of the 'eswin,hsp-sp-csr' attribute has been modified.

Fixes: 888bd0eca9 ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
Reported-by: Rob Herring (Arm) <robh@kernel.org>
Closes: https://lore.kernel.org/all/176096011380.22917.1988679321096076522.robh@kernel.org/
Signed-off-by: Shangjuan Wei <weishangjuan@eswincomputing.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251104073305.299-1-weishangjuan@eswincomputing.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Shangjuan Wei 2025-11-04 15:33:05 +08:00 committed by Jakub Kicinski
parent 9158447f09
commit 0567c84d68
1 changed files with 11 additions and 9 deletions
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20
Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
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@ -69,17 +69,19 @@ properties:
enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
eswin,hsp-sp-csr:
description:
HSP CSR is to control and get status of different high-speed peripherals
(such as Ethernet, USB, SATA, etc.) via register, which can tune
board-level's parameters of PHY, etc.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- description: Phandle to HSP(High-Speed Peripheral) device
- description: Offset of phy control register for internal
or external clock selection
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
description: |
High-Speed Peripheral device needed to configure clock selection,
clock low-power mode and clock delay.
- items:
- description: Phandle to HSP(High-Speed Peripheral) device
- description: Offset of phy control register for internal
or external clock selection
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
required:
- compatible